ZL8101ALAF datasheet(13/36 Pages) RENESAS

13 / 36 page

ZL8101

FN7832 Rev 1.00

Page 13 of 36

July 13, 2012

RESISTOR SETTINGS

This method allows a greater range of adjustability when

connecting a finite value resistor (in a specified range) between

the multi-mode pin and SGND. Standard 1% resistor values are

used, and only every fourth E96 resistor value is used so the

device can reliably recognize the value of resistance connected

to the pin while eliminating the error associated with the resistor

accuracy. Up to 31 unique selections are available using a single

resistor.

I2C/SMBUS METHOD

Almost all ZL8101 functions can be configured via the I2C/SMBus

interface using standard PMBus commands. Any value that has

been configured using the pin-strap or resistor setting methods can

also be re-configured and/or verified via the I2C/SMBus. See

Application Note AN2033 for more details.

The SMBus device address and VOUT_MAX are the only

parameters that must be set by external pins. All other device

parameters can be set via the I2C/SMBus. The device address is

set using the SA0 and SA1 pins. VOUT_MAX is set to 10% greater

than the voltage set by the V0 and V1 pins.

Power Conversion Functional

Description

Internal Bias Regulators and Input Supply

Connections

The ZL8101 employs two internal low dropout (LDO) regulators to

supply bias voltages for internal circuitry, allowing it to operate from

a single input supply. The internal bias regulators are as follows:

• VR: The VR LDO provides a regulated 5V bias supply for the

MOSFET pre-driver circuits. It is powered from the VDD pin. A

4.7 to 10µF filter capacitor is required at the VR pin. To ensure

regulator stability, capacitors outside of this range must not

be used.

• V25: The V25 LDO provides a regulated 2.5V bias supply for

the main controller circuitry. It is powered from an internal 5V

node. A 4.7 to 10µF filter capacitor is required at the V25 pin.

To ensure regulator stability capacitors outside of this range

must not be used.

When the input supply (VDD) is higher than 5.5V, the VR pin should

not be connected to any other pins. It should only have a filter

capacitor attached as shown in Figure 8. Due to the dropout voltage

associated with the VR bias regulator, the VDD pin must be

connected to the VR pin for designs operating from a supply below

5.5V. Figure 8 illustrates the required connections for both cases.

Note: the internal bias regulators are not designed to be outputs

for powering other circuitry. Do not attach external loads to any of

these pins. The multi-mode pins may be connected to the V25

pin for logic HIGH settings.

Output Voltage Selection

STANDARD MODE

The output voltage may be set to any voltage between 0.6V and

3.6V provided that the input voltage is higher than the desired

output voltage by an amount sufficient to prevent the device

from exceeding its maximum duty cycle specification. Using the

pin-strap method, VOUT can be set to any of nine standard

voltages as shown in Table 2.

The resistor setting method can be used to set the output voltage

to levels not available in Table 2. Resistors R0 and R1 are

selected to produce a specific voltage between 0.6V and 3.6V in

10mV steps. Resistor R1 provides a coarse setting and resistor

R0 provides a fine adjustment, thus eliminating the additional

errors associated with using two 1% resistors (this typically adds

1.4% error).

To set VOUT using resistors, follow the steps below to calculate an

index value and then use Table 3 to select the resistor that

corresponds to the calculated index value as follows:

1. Calculate Index1: Index1 = 4 x VOUT (VOUT in 10mV steps)

2. Round the result down to the nearest whole number.

TABLE 1. MULTI-MODE PIN CONFIGURATION

PIN TIED TO

VALUE

LOW

(Logic LOW)

<0.8VDC

OPEN

(N/C)

No connection

HIGH

(Logic HIGH)

>2.0VDC

Resistor to SGND

Set by resistor value

FIGURE 7. PIN-STRAP AND RESISTOR SETTING EXAMPLES

MULTI-MODE PIN

RSET

LOGIC

HIGH

LOGIC

LOW

OPEN

PIN-STRAP

SETTINGS

RESISTOR

SETTINGS

MULTI-MODE PIN

TABLE 2. PIN-STRAP OUTPUT VOLTAGE SETTINGS

LOW

OPEN

HIGH

LOW

0.6V

0.8V

1.0V

OPEN

1.2V

1.5V

1.8V

HIGH

2.5V

3.3V

3.6V

FIGURE 8. INPUT SUPPLY CONNECTIONS

VIN

VDD

ZL8101

VIN

VDD

ZL8101

5.5V < VIN ≤ 14V

4.5V ≤ VIN ≤ 5.5V

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