SH7145 datasheet(39/773 Pages) RENESAS

39 / 773 page

Rev. 2.0, 09/02, page xxxvii of xxxviii

Table 17.13 SH7144 Pin Functions in Each Mode (2) ...............................................................501

Table 17.14 SH7145 Pin Functions in Each Mode (1) ...............................................................505

Table 17.14 SH7145 Pin Functions in Each Mode (2) ...............................................................510

Section 18 I/O Ports

Table 18.1 Port A Data Register (PADR) Read/Write Operations .............................................556

Table 18.2 Port B Data Register (PBDR) Read/Write Operations..............................................558

Table 18.3 Port C Data Register (PCDR) Read/Write Operations..............................................560

Table 18.4 Port D Data Register (PDDR) Read/Write Operations .............................................565

Table 18.5 Port E Data Register L (PEDRL) Read/Write Operations ........................................568

Table 18.6 Port F Data Register (PFDR) Read/Write Operations ..............................................570

Section 19 Flash Memory (F-ZTAT Version)

Table 19.1 Differences between Boot Mode and User Program Mode ......................................573

Table 19.2 Pin Configuration......................................................................................................577

Table 19.3 Setting On-Board Programming Modes....................................................................581

Table 19.4 Boot Mode Operation ...............................................................................................583

Table 19.5 Peripheral Clock (P

φ) Frequencies for which Automatic Adjustment

of LSI Bit Rate is Possible ........................................................................................583

Section 22 Hitachi User Debug Interface (H-UDI)

Table 22.1 H-UDI Pins ...............................................................................................................601

Table 22.2 Serial Transfer Characteristics of H-UDI Registers..................................................602

Section 23 Advanced User Debugger (AUD)

Table 23.1 AUD Pin Configuration ............................................................................................612

Table 23.2 Ready Flag Format....................................................................................................618

Section 24 Power-Down Modes

Table 24.1 Internal Operation States in Each Mode ...................................................................622

Table 24.2 Pin Configuration......................................................................................................623

Section 26 Electrical Characteristics

Table 26.1 Absolute Maximum Ratings .....................................................................................665

Table 26.2 DC Characteristics ....................................................................................................666

Table 26.3 Permitted Output Current Values..............................................................................668

Table 26.4 Clock Timing ............................................................................................................670

Table 26.5 Control Signal Timing ..............................................................................................672

Table 26.6 Bus Timing ...............................................................................................................675

Table 26.7 Direct Memory Access Controller Timing ...............................................................679

Table 26.8 Multi-Function Timer Pulse Unit Timing .................................................................681

Table 26.9 I/O Port Timing.........................................................................................................682

Table 26.10 Watchdog Timer Timing.........................................................................................683

Table 26.11 Serial Communication Interface Timing.................................................................684

Table 26.12 I

2C Bus Interface Timing ........................................................................................686

Table 26.13 Output Enable Timing.............................................................................................687

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