LTC1743CFW datasheet(13/24 Pages) LINER

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LTC1743

1743f

APPLICATIO S I FOR ATIO

Figure 2. Equivalent Input Circuit

CSAMPLE

7pF

CPARASITIC

8pF

VDD

LTC1743

AIN

1743 F02

CSAMPLE

7pF

8pF

BIAS

VDD

AIN

–

ENC

When ENC is low, the analog input is sampled differentially

directly onto the input sample-and-hold capacitors, inside

the “Input S/H” shown in the block diagram. At the instant

that ENC transitions from low to high, the sampled input

is held. While ENC is high, the held input voltage is

buffered by the S/H amplifier which drives the first pipelined

ADC stage. The first stage acquires the output of the S/H

during this high phase of ENC. When ENC goes back low,

the first stage produces its residue which is acquired by

the second stage. At the same time, the input S/H goes

back to acquiring the analog input. When ENC goes back

high, the second stage produces its residue which is

acquired by the third stage. An identical process is re-

peated for the third stage, resulting in a third stage residue

that is sent to the fourth stage ADC for final evaluation.

Each ADC stage following the first has additional range to

accommodate flash and amplifier offset errors. Results

from all of the ADC stages are digitally delayed such that

the results can be properly combined in the correction

logic before being sent to the output buffer.

SAMPLE/HOLD OPERATION AND INPUT DRIVE

Sample Hold Operation

Figure 2 shows an equivalent circuit for the LTC1743

CMOS differential sample-and-hold. The differential ana-

log inputs are sampled directly onto sampling capacitors

(CSAMPLE) through CMOS transmission gates. This direct

capacitor sampling results in lowest possible noise for a

given sampling capacitor size. The capacitors shown

attached to each input (CPARASITIC) are the summation of

all other capacitance associated with each input.

During the sample phase when ENC/ENC is low, the

transmission gate connects the analog inputs to the sam-

pling capacitors and they charge to and track the differen-

tial input voltage. When ENC/ENC transitions from low to

high the sampled input voltage is held on the sampling

capacitors. During the hold phase when ENC/ENC is high

the sampling capacitors are disconnected from the input

and the held voltage is passed to the ADC core for

processing. As ENC/ENC transitions from high to low the

inputs are reconnected to the sampling capacitors to

acquire a new sample. Since the sampling capacitors still

hold the previous sample, a charging glitch proportional to

the change in voltage between samples will be seen at this

time. If the change between the last sample and the new

sample is small the charging glitch seen at the input will be

small. If the input change is large, such as the change seen

with input frequencies near Nyquist, then a larger charging

glitch will be seen.

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