MAX5418NETA datasheet(4/15 Pages) MAXIM

4 / 15 page

256-Tap, Nonvolatile, I2C-Interface,

Digital Potentiometers

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Note 1:

The DNL and INL are measured with the potentiometer configured as a voltage-divider with H = VDD and L = GND. The

wiper terminal is unloaded and measured with a high-input-impedance voltmeter.

Note 2:

The DNL and INL are measured with the potentiometer configured as a variable resistor. H is unconnected and L = GND.

For the 5V condition, the wiper terminal is driven with a source current of 80µA for the 50k

Ω configuration, 40µA for the

100k

Ω configuration, and 20µA for the 200kΩ configuration. For the 3V condition, the wiper terminal is driven with a source

current of 40µA for the 50k

Ω configuration, 20µA for the 100kΩ configuration, and 10µA for the 200kΩ configuration.

Note 3:

The wiper resistance is measured using the source currents given in Note 2. For operation to VDD = 2.7V, see Wiper

Resistance vs. Temperature in the Typical Operating Characteristics.

Note 4:

The device draws higher supply current when the digital inputs are driven with voltages between (VDD - 0.5V) and (GND +

0.5V). See Supply Current vs. Digital Input Voltage in the Typical Operating Characteristics.

Note 5:

Wiper at midscale with a 10pF load (DC measurement). L = GND; an AC source is applied to H; and the W output is mea-

sured. A 3dB bandwidth occurs when the AC W/H value is 3dB lower than the DC W/H value.

Note 6:

The programming current operates only during power-up and NV writes.

Note 7:

SCL clock period includes rise and fall times tR and tF. All digital input signals are specified with tR = tF = 2ns and timed

from a voltage level of (VIL + VIH) / 2.

Note 8:

Wiper settling time is the worst-case 0% to 50% rise time measured between consecutive wiper positions. H = VDD,

L = GND, and the wiper terminal is unloaded and measured with a 10pF oscilloscope probe (see the Typical Operating

Characteristics for the tap-to-tap switching transient).

Note 9:

An appropriate bus pullup resistance must be selected depending on board capacitance. Refer to the document linked to

this web address: www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf.

Note 10: The idle time begins from the initiation of the stop pulse.

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Data Setup Time

tSU-DAT

100

Data Hold Time

tHD-DAT

0.9

µs

SDA, SCL Rise Time

300

SDA, SCL Fall Time

300

Setup Time for STOP Condition

tSU-STO

0.6

µs

Bus Free Time Between STOP

and START Condition

tBUF

Minimum power-up rate = 0.2V/ms

1.3

µs

Pulse Width of Spike Suppressed

tSP

Maximum Capacitive Load for

Each Bus Line

(Note 9)

400

Write NV Register Busy Time

tBUSY

(Note 10)

TIMING CHARACTERISTICS (continued)

(VDD = +2.7V to +5.25V, H = VDD, L = GND, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VDD = +5V, TA =

+25°C. See Figures 1 and 2.) (Note 7)

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