TAS5805MPWPR datasheet(30/86 Pages) TI1

30 / 86 page

Acknowledge

Start

Condition

2C Device Address

and R/W Bit

Subaddress

First Data Byte

Other Data Byte

Last Data Byte

Stop

Condition

ACK

D0 ACK D7

ACK

R/W ACK

Acknowledge

Start

Condition

2C Device Address

and R/W Bit

Subaddress

Data Byte

Stop

Condition

ACK

A0 ACK

A0 R/W ACK A7

TAS5805M

SLASEH5A – MAY 2018 – REVISED JULY 2018

www.ti.com

Product Folder Links: TAS5805M

Submit Documentation Feedback

9.5 Programming and Control

9.5.1

I2 C Serial Communication Bus

The device has a bidirectional serial control interface that is compatible with the Inter IC ( I2)C bus protocol and

supports 100 and 400-kHz data transfer rates for random and sequential write and read operations as a slave

device. Because the TAS5805M register map and DSP memory spans multi pages, the user should change from

page to page before writing individual register or DSP memory. Changing from page to page is accomplished via

9.5.2 Slave Address

The TAS5805M device has 7 bits for the slave address. The first five bits (MSBs) of the slave address are

factory preset to 01011(0x5x). The next two bits of address byte are the device select bits which can be user-

defined by ADR pin in Table 4.

Table 4. I2 C Slave Address Configuration

ADR PIN Configuration

MSBs

User Define

LSB

4.7k

Ω to DVDD

R/W

15k

Ω to DVDD

R/W

47k

Ω to DVDD

R/W

120k

Ω to DVDD

R/W

9.5.2.1 Random Write

As shown in Figure 64, a single-byte data-write transfer begins with the master device transmitting a start

condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of

the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address

and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte

corresponding to the internal memory address being accessed. After receiving the address byte, the device

again responds with an acknowledge bit. Next, the master device transmits the data byte to be written to the

memory address being accessed. After receiving the data byte, the device again responds with an acknowledge

bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

Figure 64. Random Write Transfer

9.5.2.2 Sequential Write

A sequential data-write transfer is identical to a single-byte data-write transfer except that multiple data bytes are

transmitted by the master to the device as shown in Figure 65. After receiving each data byte, the device

responds with an acknowledge bit and the I2 subaddress is automatically incremented by one.

Figure 65. Sequential Write Transfer

TAS5805MPWPR Datasheet(PDF) 30 Page - Texas Instruments

TAS5805MPWPR Datasheet(HTML) 30 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86

Datasheet Download

Link URL