MPC9352

TIMING SOLUTIONS

13

MOTOROLA

offset) test reference

Figure 16. Output Duty Cycle (DC)

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

GND

GND

GND

GND

GND

CCLK

FB_IN

CCLK

FB_IN

random sample of cycles

Figure 17. I/O Jitter

Figure 18. Cycle–to–cycle Jitter

Figure 19. Period Jitter

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

2.4

1.8V

0.55

0.6V

Figure 20. Output Transition Time Test Reference

Freescale Semiconductor, Inc.

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