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TMUX1072

SCDS382 – APRIL 2018

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Copyright © 2018, Texas Instruments Incorporated

10 Power Supply Recommendations

Power to the device is supplied through the VCC pin. TI recommends placing a 100-nF bypass capacitor as

close to the supply pin VCC as possible to help smooth out lower frequency noise to provide better load

regulation across the frequency spectrum.

11 Layout

11.1 Layout Guidelines

1. Place supply bypass capacitors as close to VCC pin as possible and avoid placing the bypass caps near the

signal traces.

2. The high-speed traces should always be of equal length and must be no more than 4 inches; otherwise, the

eye diagram performance may be degraded.

3. Route the high-speed signals using a minimum of vias and corners which will reduce signal reflections and

impedance changes. When a via must be used, increase the clearance size around it to minimize its

capacitance. Each via introduces discontinuities in the transmission line of the signal and increases the

chance of picking up interference from the other layers of the board. Be careful when designing test points

on twisted pair lines; through-hole pins are not recommended.

4. When it becomes necessary to turn 90°, use two 45° turns or an arc instead of making a single 90° turn. This

reduces reflections on the signal traces by minimizing impedance discontinuities.

5. Do not route signal traces under or near crystals, oscillators, clock signal generators, switching regulators,

mounting holes, magnetic devices, or IC’s that use or duplicate clock signals.

6. Avoid stubs on the high-speed signals because they cause signal reflections.

7. Route all high-speed signal traces over continuous planes (VCC or GND), with no interruptions.

8. Avoid crossing over anti-etch, commonly found with plane splits.

9. For high frequency systems, a printed circuit board with at least four layers is recommended: two signal

layers separated by a ground layer and a power layer. The majority of signal traces should run on a single

layer, preferably Signal 1. Immediately next to this layer should be the GND plane, which is solid with no

cuts. Avoid running signal traces across a split in the ground or power plane. When running across split

planes is unavoidable, sufficient decoupling must be used. Minimizing the number of signal vias reduces EMI

by reducing inductance at high frequencies. For more information on layout guidelines, see High Speed

Layout Guidelines (SCAA082)