PEX8605, PCI Express Gen 2 Switch, 4 Lanes, 4 Ports

© PLX Technology, www.plxtech.com

Page 1 of 3

8/17/2011, Version 1.1

Highlights

o

4-lane, 4-port PCIe Gen2 switch

 Integrate 5.0 GT/s SerDes

o

10 x 10mm

package

o

Typical Power: 0.8 Watts

o

Standards Compliant

 PCI Express Base Specification, r2.1

(backwards compatible w/ PCIe

1.0a/1.1)

 PCI Power Management Spec, r1.2

 Microsoft Windows 7 Compliant

 Dynamic SerDes speed control

o

High Performance

 Non-blocking switch fabric

 Full line rate on all ports

 Packet Cut-Thru with 250ns max

packet latency (x1 to x1)

 256B Max Payload Size

o

Flexible Configuration

 Ports configurable as x1, x2

 Registers configurable with strapping

pins, EEPROM, I

 Reference Clock Buffered Output

signals for downstream ports

 Lane and polarity reversal

 Compatible with PCIe 1.0a PM

o

Quality of Service (QoS)

 Eight traffic classes per port

 Round-robin source port arbitration

 Relaxed PCI Ordering

o

Reliability, Availability,

Serviceability

 visionPAK™

• Per Port Performance Monitoring

• Per port payload & header counters

• SerDes Eye Capture

• Error Injection and Loopback

(Hot-Plug Controller on every port)

 Data Path parity

 Memory (RAM) Error Correction

signals

 INTA# and FATAL_ERR#

 Advanced Error Reporting

 Port Status bits and GPIO available

 Per port error diagnostics

 JTAG AC/DC boundary scan

o

Power Management

 WAKE#, Beacon, Vaux support

enabling users to add scalable high bandwidth non-blocking interconnection

to a wide variety of applications including control plane applications,

consumer applications and embedded systems. The PEX8605 is well suited

for fan-out and peer-to-peer applications.

Low Packet Latency & High Performance

The PEX8605 architecture supports packet cut-thru with a maximum latency of

250ns in x1 to x1 configuration. This, combined with low power consumption

and non-blocking internal switch architecture, provides full line rate on all ports

for low-power applications such as consumer and embedded. The low latency

enables applications to achieve high throughput and performance. In addition to

low latency, the device supports a max payload size of 256 bytes.

Data Integrity

The PEX8605 provides end-to-end CRC protection (ECRC) and Poison bit

support to enable designs that require guaranteed error-free packets. PLX also

supports data path parity and memory (RAM) error correction as packets pass

through the switch.

Power Management and Clock Buffering

The PEX8605 supports the following power management states: L0, L0s, L1,

L2/L3 Ready, L2 and L3. Moreover, the PEX8605 supports Vaux along with the

external signal WAKE# and the in-band Beacon for the PCIe endpoints to use to

inform the system host to exit the low power savings mode.

The PEX 8605 supports three pairs of PCI Express-compliant, 100MHz, buffered

HCSL output clocks, one pair for each downstream port of the switch. Each

clock output pair can be disabled by software or serial EEPROM when not in

use, for additional power savings. This feature greatly reduces system BOM cost

by eliminating the need for extra clock buffers on the PCB.

Interoperability

The PEX8605 is designed to be fully compliant with the PCI Express Base

Specification r2.1 and is backwards compatible to PCI Express Base

Specification r1.1 and r1.0a. Additionally each port supports auto-negotiation and

polarity reversal. Furthermore, the PEX8605 is designed for Microsoft Windows

7 compliance. All PLX switches undergo thorough interoperability testing in

PLX’s Interoperability Lab and compliance testing at the PCI-SIG plug-fest to

ensure compatibility with PCI Express devices in the market.

Device Operation Configuration Flexibility

The PEX8605 provides several ways to configure its operations. The device can

be configured through strapping pins, I

and/or an optional serial EEPROM. This allows for easy debug during the

development phase and functional monitoring during the operation phase.