LTC2230 datasheet(14/28 Pages) LINER

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LTC2230/LTC2231

22301p

FUNCTIONAL BLOCK DIAGRA

PI FU CTIO S

SENSE (Pin 59): Reference Programming Pin. Connecting

SENSE to VCM selects the internal reference and a ±0.5V

input range. VDD selects the internal reference and a ±1V

input range. An external reference greater than 0.5V and

less than 1V applied to SENSE selects an input range of

±VSENSE. ±1V is the largest valid input range.

VCM (Pin 60): 1.6V Output and Input Common Mode Bias.

Bypass to ground with 2.2µF ceramic chip capacitor.

GND (Exposed Pad): ADC Power Ground. The exposed

pad on the bottom of the package needs to be soldered to

ground.

DIFF

REF

AMP

REF

BUF

2.2µF

1µF

0.1µF0.1µF

1µF

INTERNAL CLOCK SIGNALS

REFH

REFL

DIFFERENTIAL

INPUT

LOW JITTER

CLOCK

DRIVER

RANGE

SELECT

1.6V

REFERENCE

FIRST PIPELINED

ADC STAGE

(4 BITS)

FIFTH PIPELINED

ADC STAGE

(3 BITS)

FOURTH PIPELINED

ADC STAGE

(3 BITS)

SECOND PIPELINED

ADC STAGE

(3 BITS)

ENC+

REFHA

REFLB

REFLA REFHB

ENC–

SHIFT REGISTER

AND CORRECTION

OEL

M0DE

OGND

OVDD

CLKOUT

22201 F01

INPUT

S/H

SENSE

VCM

AIN

–

AIN

2.2µF

THIRD PIPELINED

ADC STAGE

(3 BITS)

OUTPUT

DRIVERS

CONTROL

LOGIC

LVDS SHDN

•

–

Figure 1. Functional Block Diagram

N – 5

N – 4

N – 3

N – 2

N – 1

tAP

N + 1

N + 2

N + 4

N + 3

ANALOG

INPUT

ENC–

ENC+

CLOCKOUT –

CLOCKOUT+

D0-D9, OF

22201 TD01

LVDS Output Mode Timing

All Outputs Are Differential and Have LVDS Levels

TI I G DIAGRA S

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