AD1934_13 datasheet(23/28 Pages) AD

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Data Sheet

AD1934

Rev. D | Page 23 of 28

AUXILIARY TDM PORT CONTROL REGISTERS

Table 23. Auxiliary TDM Control 0

Bit

Value

Function

Description

1:0

Word width

Reserved

4:2

000

SDATA delay (BCLK periods)

001

010

011

100

101

Reserved

110

Reserved

111

Reserved

6:5

Reserved

Serial format

Reserved

DAC aux mode

Reserved

Latch in midcycle (normal)

BCLK active edge (TDM in)

Latch in at end of cycle (pipeline)

Table 24. Auxiliary TDM Control 1

Bit

Value

Function

Description

50/50 (allows 32/24/20/16 BCLK/channel)

LRCLK format

Pulse (32 BCLK/channel)

Drive out on falling edge (DEF)

BCLK polarity

Drive out on rising edge

Left low

LRCLK polarity

Left high

Slave

LRCLK master/slave

Master

5:4

BCLKs per frame

128

256

512

Slave

BCLK master/slave

Master

AUXTDMBCLK pin

BCLK source

Internally generated

ADDITIONAL MODES

The AD1934 offers several additional modes for board level

design enhancements. To reduce the EMI in board level design,

serial data can be transmitted without an explicit BCLK. See

Figure 19 for an example of a DAC TDM data transmission

mode that does not require high speed DBCLK. This configuration

is applicable when the AD1934 master clock is generated by the

PLL with the DLRCLK as the PLL reference frequency.

To relax the requirement for the setup time of the AD1934 in

cases of high speed TDM data transmission, the AD1934 can

latch in the data using the falling edge of DBCLK. This

effectively dedicates the entire BCLK period to the setup time.

This mode is useful in cases where the source has a large delay

time in the serial data driver. Figure 20 shows this pipeline

mode of data transmission.

Both the BLCK-less and pipeline modes are available.

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