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WM8950 Datasheet(PDF) 40 Page - Wolfson Microelectronics plc |
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WM8950 Datasheet(HTML) 40 Page - Wolfson Microelectronics plc |
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40 / 52 page  WM8950 Preliminary Technical Data w PTD Rev 2.1 June 2005 40 BIASEN REGISTER ADDRESS BIT LABEL DEFAULT DESCRIPTION R1 Power management 1 3 BIASEN 0 Analogue amplifier bias control Table 36 BIASEN Control ESTIMATED SUPPLY CURRENTS When the ADC is enabled it is estimated that approximately 4mA will be drawn from DCVDD when fs=48kHz (This will be lower at lower sample rates). When the PLL is enabled an additional 700 microamps will be drawn from DCVDD. Table 59 shows the estimated 3.3V AVDD current drawn by various circuits, by register bit. REGISTER BIT AVDD CURRENT (MILLIAMPS) BUFDCOPEN 0.1 PLLEN 1.4 (with clocks applied) MICBEN 0.5 BIASEN 0.3 BUFIOEN 0.1 VMIDSEL 10K=>0.3, less than 0.1 for 100k/500k INPPGAEN 0.2 ADCEN x64 (ADCOSR=0)=>2.6, x128 (ADCOSR=1)=>4.9 Table 37 AVDD Supply Current |
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