© 2007 Fairchild Semiconductor Corporation

www.fairchildsemi.com

FSSD07 Rev. 1.0.2

2

Pin Configuration

12

11

6

7

8

9

10

15

17

18

19

VDDC

GND

1

224

23

13

14

3

4

5

20

21

22

DAT[2]

1CLK

DAT[3]

CLK

DAT[0]

CMD

DAT[1]

2CMD

VDDH2

1DAT[1]

2DAT[2]

VDDH1

1DAT[0]

2DAT[3]

16

DAT[3]

CMD

VDDC

GND

CLK

1CLK

2CMD

DAT[0]

1DAT[0]

1DAT[1]

2DAT[3]

2DAT[2]

1

2

3

4

5

6

24

10

9

8

7

14

13

12

11

19

18

17

16

15

23

22

21

20

Figure 2.

MLP Pin Assignments

Figure 3.

UMLP Pin Assignments

Pin Definitions

Pin# MLP

Pin# UMLP

Name

Description

1

22

1DAT[2]

SDIO Common Port

2

23

OE

Output Enable (Active HIGH)

3

24

DAT[2]

SDIO Common Port

4

1

DAT[3]

5

2

CMD

6

3

VDDC

Power Supply (SDIO Peripheral Card Port)

7

4

GND

Ground

8

5

CLK

Clock Path Port

9

6

DAT[0]

SDIO Common Port

10

7

DAT[1]

11

8

S

Select Pin

12

9

2DAT[1]

Host Common Port

13

10

2DAT[0]

14

11

2CLK

Clock Path Port

15

12

VDDH2

Power Supply (Host Port)

16

13

2CMD

Host Common Port

17

14

2DAT[3]

18

15

2DAT[2]

19

16

1DAT[1]

20

17

1DAT[0]

21

18

1CLK

Clock Path Port

22

19

VDDH1

Power Supply (SDIO Host Port)

23

20

1CMD

Host Common Port

24

21

1DAT[3]

Truth Table

OE

S

Function

HIGH

LOW

1CMD, 1CLK, 1DAT[3:0] connected to CMD, CLK, DAT[3:0]

HIGH

HIGH

2CMD, 2CLK,2DAT[3:0] connected to CMD, CLK, DAT[3:0]

LOW

X

CMD, DAT[3:0] ports high impedance; CLK is function of selected nCLK