ADCLK950

Data Sheet

Rev. B | Page 6 of 12

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

IN_SEL

CLK0

CLK0

CLK1

CLK1

NC

Q5

Q5

Q4

Q4

NC

NC

NC

1

2

3

4

5

6

7

8

9

10

23

24

25

26

27

28

29

30

22

21

ADCLK950

TOP VIEW

(Not to Scale)

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

Figure 2. Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

IN_SEL

Input Select. Logic 0 selects CLK0 and CLK0 inputs. Logic 1 selects CLK1 and CLK1 inputs.

2

CLK0

Differential Input (Positive) 0.

3

CLK0

Differential Input (Negative) 0.

4

V

Reference Voltage. Reference voltage for biasing ac-coupled CLK0 and CLK0 inputs.

5

V

Center Tap. Center tap of a 100 Ω input resistor for CLK0 and CLK0 inputs.

6

CLK1

Differential Input (Positive) 1.

7

CLK1

Differential Input (Negative) 1.

8

V

Center Tap. Center tap of a 100 Ω input resistor for CLK1 and CLK1 inputs.

9

V

Reference Voltage. Reference voltage for biasing ac-coupled CLK1 and CLK1 inputs.

10

V

EE

Negative Supply Pin.

11, 20, 21,

30, 31, 40

V

CC

Positive Supply Pin.

12, 13

Q9, Q9

Differential LVPECL Outputs.

14, 15

Q8, Q8

Differential LVPECL Outputs.

16, 17

Q7, Q7

Differential LVPECL Outputs.

18, 19

Q6, Q6

Differential LVPECL Outputs.

22, 23, 28,

29

NC

No Connection

24, 25

Q5, Q5

Differential LVPECL Outputs.

26, 27

Q4, Q4

Differential LVPECL Outputs.

32, 33

Q3, Q3

Differential LVPECL Outputs.

34, 35

Q2, Q2

Differential LVPECL Outputs.

36, 37

Q1, Q1

Differential LVPECL Outputs.

38, 39

Q0, Q0

Differential LVPECL Outputs.

EPAD

Exposed Pad. The EPAD must be soldered to the V