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AD9543 Datasheet(PDF) 22 Page - Analog Devices

Part # AD9543
Description  Quad Input, 10-Output, Dual DPLL/IEEE 1588 Synchronizer and Jitter Cleaner
PDF  66 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9543 Datasheet(HTML) 22 Page - Analog Devices

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AD9543
Data Sheet
Rev. 0 | Page 22 of 66
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
M3
4
5
6
7
25
OUT0AN
26
27
28
29
30
31
32
33
34
35
36
SDO/M5
8
9
10
11
12
OUT1AP
SDIO/SDA
CSB/M6
OUT0AP
VDDIOA
SCLK/SCL
VDD
VDD
VDD
LF0
LDO0
PIN 1
INDICATOR
AD9543
TOP VIEW
(Not to Scale)
VDD
M1
OUT1AN
M2
VDD
LDO1
VDD
LF1
M0
VDDIOB
NOTES
1. EXPOSED PAD. THE EXPOSED PAD IS THE GROUND CONNECTION
ON THE CHIP. THE EXPOSED PAD MUST BE SOLDERED TO THE
ANALOG GROUND OF THE PCB TO ENSURE PROPER
FUNCTIONALITY AND FOR HEAT DISSIPATION, NOISE, AND
MECHANICAL STRENGTH BENEFITS.
2. DNC = DO NOT CONNECT. LEAVE THESE PINS FLOATING.
Figure 2. Pin Configuration
Table 26. Pin Function Descriptions
Pin No.
Mnemonic
Input/
Output
Pin Type
Description
1
SDO/M5
Output
CMOS
Serial Data Output (SDO). This pin is for reading serial data in 4-wire SPI
mode. Changes to the VDDIOA supply voltage affect the VIH and VOH
values for this pin.
Configurable Input/Output (M5). This pin is a status and control pin
when the device is not in 4-wire SPI mode.
2
SCLK/SCL
Input
CMOS
Serial Programming Clock (SCLK) Pin in SPI Mode. Changes to the
VDDIOA supply voltage affect the VIH and VOH values for this pin.
Serial Clock Pin (SCL) in I2C Mode. Changes to the VDDIOA supply
voltage affect the VIH and VOH values for this pin.
3
VDDIOA
Input
Power
Serial Port Power Supply. The valid supply voltage is 1.8 V, 2.5 V, or 3.3 V.
The VDDIOA pin can be connected to the VDD supply bus if 1.8 V
operation is desired.
4
SDIO/SDA
Input/
output
CMOS
Serial Data Input/Output (SDIO) in SPI Mode. Write data to this pin in
4-wire SPI mode. This pin has no internal pull-up or pull-down resistor.
Changes to the VDDIOA supply voltage affect the VIH and VOH values for
this pin.
Serial Data Pin in I2C Mode (SDA).
5
CSB/M6
Input/
output
CMOS
Chip Select (CSB) in SPI Mode. Active low input. Maintain a Logic 0
level on this pin when programming the device in SPI mode. This pin
has an internal 10 kΩ pull-up resistor. Changes to the VDDIOA supply
voltage affect the VIH and VOH values for this pin.
Configurable Input/Output (M6). This pin is a status and control pin
when the device is not in SPI mode.
6, 9, 10, 13, 19,
20, 24, 27, 28,
31, 40, 41, 45
VDD
Input
Power
1.8 V Power Supply.
7
LDO0
Input
LDO bypass
APLL0 Loop Filter Voltage Regulator. Connect a 0.22 μF capacitor from
this pin to ground. This pin is the ac ground reference for the
integrated APLL0 loop filter.
8
LF0
Input/
output
Loop filter
for APLL0
Loop Filter Node for APLL0. Connect a 3.9 nF capacitor from this pin to
Pin 7 (LDO0).



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