AD9552 datasheet(6/32 Pages) AD

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AD9552

Data Sheet

Rev. E | Page 6 of 32

SERIAL CONTROL PORT

Table 5.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

Input Logic 1 Voltage

1.6

Input Logic 0 Voltage

0.5

Input Logic 1 Current

0.03

µA

Input Logic 0 Current

µA

Input Capacitance

SCLK

Input Logic 1 Voltage

1.6

Input Logic 0 Voltage

0.5

Input Logic 1 Current

µA

Input Logic 0 Current

0.03

µA

Input Capacitance

SDIO

Input

Input Logic 1 Voltage

1.6

Input Logic 0 Voltage

0.5

Input Logic 1 Current

µA

Input Logic 0 Current

µA

Input Capacitance

Output

Output Logic 1 Voltage

2.8

1 mA load current

Output Logic 0 Voltage

0.3

1 mA load current

SERIAL CONTROL PORT TIMING

Table 6.

Parameter

Limit

Unit

SCLK

Clock Rate, 1/t

CLK

MHz max

Pulse Width High, t

HIGH

ns min

Pulse Width Low, t

LOW

ns min

SDIO to SCLK Setup, t

ns min

SCLK to SDIO Hold, t

ns min

SCLK to Valid SDIO, t

ns max

CS to SCLK Setup (t

S) and Hold (tH)

ns min

CS Minimum Pulse Width High

6.4

ns min

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