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AD9510 Datasheet(PDF) 6 Page - Analog Devices

Part # AD9510
Description  1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
PDF  56 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9510 Datasheet(HTML) 6 Page - Analog Devices

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AD9510
Data Sheet
Rev. C | Page 6 of 56
CLOCK OUTPUTS
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL CLOCK OUTPUTS
Termination = 50 Ω to VS − 2 V
OUT0, OUT1, OUT2, OUT3;
Differential
Output level Register 0x3C, Register 0x3D,
Register 0x3E, Register 0x3F[3:2] = 10b
Output Frequency
1200
MHz
See Figure 21
Output High Voltage
VOH
VS − 1.22
VS − 0.98
VS − 0.93
V
Output Low Voltage
VOL
VS − 2.10
VS − 1.80
VS − 1.67
V
Output Differential Voltage
VOD
660
810
965
mV
LVDS CLOCK OUTPUTS
Termination = 100 Ω differential; default
OUT4, OUT5, OUT6, OUT7;
Differential
Output level Register 0x40, Register 0x41,
Register 0x42, Register 0x43[2:1] = 01b
3.5 mA termination current
Output Frequency
800
MHz
See Figure 22
Differential Output Voltage
VOD
250
360
450
mV
Delta VOD
25
mV
Output Offset Voltage
VOS
1.125
1.23
1.375
V
Delta VOS
25
mV
Short-Circuit Current
ISA, ISB
14
24
mA
Output shorted to GND
CMOS CLOCK OUTPUTS
OUT4, OUT5, OUT6, OUT7
Single-ended measurements, B outputs:
inverted, termination open
Output Frequency
250
MHz
With 5 pF load each output, see Figure 23
Output Voltage High
VOH
VS − 0.1
V
At 1 mA load
Output Voltage Low
VOL
0.1
V
At 1 mA load
TIMING CHARACTERISTICS
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
LVPECL
Termination = 50 Ω to VS − 2 V; output level
Register 0x3C, Register 0x3D, Register 0x3E,
Register 0x3F[3:2] = 10b
Output Rise Time
tRP
130
180
ps
20% to 80%, measured differentially
Output Fall Time
tFP
130
180
ps
80% to 20%, measured differentially
PROPAGATION DELAY, CLK-TO-LVPECL OUT1
tPECL
Divide = Bypass
335
490
635
ps
Divide = 2 − 32
375
545
695
ps
Variation with Temperature
0.5
ps/°C
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part2
tSKP
−5
+30
+85
ps
OUT2 to OUT3 on Same Part2
tSKP
15
45
80
ps
All LVPECL OUTs on Same Part2
tSKP
90
130
180
ps
All LVPECL OUTs Across Multiple Parts3
tSKP_AB
275
ps
Same LVPECL OUT Across Multiple
Parts3
tSKP_AB
130
ps
LVDS
Termination = 100 Ω differential; output level
Register 0x40, Register 0x41, Register 0x42,
Register 0x43[2:1] = 01b; 3.5 mA termination
current
Output Rise Time
tRL
200
350
ps
20% to 80%, measured differentially
Output Fall Time
tFL
210
350
ps
80% to 20%, measured differentially



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