AD9540BCPZ datasheet(22/32 Pages) AD

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AD9540

Data Sheet

Rev. C | Page 22 of 32

SERIAL PORT OPERATION

An AD9540 serial data port communication cycle has two

phases. Phase 1 is the instruction cycle, writing an instruction

byte to the AD9540, coincident with the first eight SCLK rising

edges. The instruction byte provides the AD9540 serial port

controller with information regarding the data transfer cycle,

which is Phase 2 of the communication cycle. The Phase 1

instruction byte defines the serial address of the register being

accessed and whether the upcoming data transfer is read or

write.

The first eight SCLK rising edges of each communication cycle

are used to write the instruction byte into the AD9540. The

remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the AD9540

and the system controller.

The number of bytes transferred during Phase 2 of the commu-

nication cycle is a function of the register being accessed. For

example, when accessing Control Function Register 2, which is four

bytes wide, Phase 2 requires that four bytes be transferred. If

accessing a frequency tuning word, which is six bytes wide,

Phase 2 requires that six bytes be transferred. After transferring

all data bytes per the instruction, the communication cycle is

completed.

At the completion of any communication cycle, the AD9540

serial port controller expects the next eight rising SCLK edges

to be the instruction byte of the next communication cycle. All

data input to the AD9540 is registered on the rising edge of

SCLK. All data is driven out of the AD9540 on the falling edge

of SCLK. Figure 39 through Figure 42 are useful in understand-

ing the general operation of the AD9540 serial port.

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

Figure 39. Serial Port Write Timing—Clock Stall Low

DON'T CARE

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

SDO

Figure 40. 3-Wire Serial Port Read Timing—Clock Stall Low

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

Figure 41. Serial Port Write Timing—Clock Stall High

INSTRUCTION CYCLE

SCLK

SDI/O

DATA TRANSFER CYCLE

Figure 42. 2-Wire Serial Port Read Timing—Clock Stall High

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