AD9554BCPZ datasheet(4/116 Pages) AD

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AD9554

Data Sheet

Rev. D | Page 4 of 116

REVISION HISTORY

3/2017—Rev. C to Rev. D

Changes to Chip Power and Startup Section .............................. 25

Changes to Figure 26...................................................................... 26

10/2016—Rev. B to Rev. C

Changes to Multifunction Pins at Reset/Power-Up Section

and Table 21..................................................................................... 25

Changes to Figure 29...................................................................... 29

Changes to the Important Update to EEPROM Programing

Sequence Section ............................................................................ 48

Changes to Table 71 and Table 73 ................................................ 82

6/2016—Rev. A to Rev. B

Changes to Device Register Programming Using a Register

Setup File Section ........................................................................... 25

Added Figure 26 to Figure 29; Renumbered Sequentially ........ 26

Added Note 1, Table 69.................................................................. 81

Changes to Bit 1 Description, Table 98........................................ 90

8/2014—Rev. 0 to Rev. A

Changes to Applications and General Description Sections ...... 1

Added Output Frequency of 0.430 MHz (Min) and

941 MHz (Max); Table 8 ................................................................ 10

Added Bandwidth (fREF = 19.44 MHz; fOUT = 156.25 MHz;

fLOOP = 50 Hz) Parameters; Table 18 ............................................. 15

Changes to Figure 3........................................................................ 21

Changes to Figure 24 Caption....................................................... 24

Changes to Table 21 and Device Register Programming Using a

Changes to Overview Section....................................................... 30

Changes to DPLL Overview Section and Figure 27 .................. 32

Changes to System Clock (SYSCLK) Section ............................. 35

Changes to APLL Calibration Section......................................... 37

Changes to P Dividers and Output Amplitude and

Power-Down Sections.................................................................... 38

Changes to EEPROM Overview Section and Figure 32............ 41

Changes to Second Paragraph of Serial Port Control Section.. 45

Changes to Write Section, Address Ascension Section and

Table 25 ............................................................................................ 46

Changes to Data Transfer Process Section.................................. 48

Changes to Write Detect Registers Section................................. 51

Changes to Table 32 ....................................................................... 54

Changes to Table 47 ....................................................................... 71

Changes to Table 61 and Table 62 ................................................ 74

Changes to Table 68 ....................................................................... 76

Changes to Table 71 ....................................................................... 78

Changes to Table 76 ....................................................................... 79

Changes to Table 78 and Table 79 ................................................ 80

Changes to Table 100 ..................................................................... 87

Changes to Table 118 ..................................................................... 94

Changes to Table 121 ..................................................................... 96

Changes to Table 126 ..................................................................... 99

Changes to Table 155 ................................................................... 110

4/2014—Revision 0: Initial Version

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