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ATF750LVC Datasheet(PDF) 1 Page - ATMEL Corporation |
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ATF750LVC Datasheet(HTML) 1 Page - ATMEL Corporation |
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1 / 14 page ![]() 1 Features • 3.0V to 3.6V Operating Range • Advanced, High-speed, Electrically-erasable Programmable Logic Device – Superset of 22V10 – Enhanced Logic Flexibility – Architecturally Compatible with ATV750B and ATV750 Software and Hardware • D- or T-type Flip-flop • Product Term or Direct Input Pin Clocking • 15 ns Maximum Pin-to-pin Delay with 3V Operation • Highest Density Programmable Logic Available in 24-pin Package – Advanced Electrically-erasable Technology – Reprogrammable – 100% Tested • Increased Logic Flexibility – 42 Array Inputs, 20 Sum Terms and 20 Flip-flops • Enhanced Output Logic Flexibility – All 20 Flip-flops Feed Back Internally – 10 Flip-flops are also Available as Outputs • Programmable Pin-keeper Circuits • Dual-in-line and Surface Mount Package in Standard Pinouts • Commercial and Industrial Temperature Ranges • 20-year Data Retention • 2000V ESD Protection • 1000 Erase/Write Cycles Block Diagram Description The Atmel “750” architecture is twice as powerful as most other 24-pin programmable logic devices. Increased product terms, sum terms, flip-flops and output logic configu- rations translate into more usable gates. High-speed logic and uniform, predictable delays guarantee fast in-system performance. The ATF750LVC is a high-performance PROGRAMMABLE INTERCONNECT AND COMBINATORIAL LOGIC ARRAY LOGIC OPTION (UP T0 20 FLIP-FLOPS) OUTPUT OPTION 4TO 8 PRODUCT TERMS (OE PRODUCT TERMS) 10 I/O PINS 12 INPUT PINS (CLOCK PIN) Rev. 1447D–03/01 High-speed Complex Programmable Logic Device ATF750LVC Pin Configurations Pin Name Function CLK Clock IN Logic Inputs I/O Bi-directional Buffers GND Ground VCC 3V Supply (continued) DIP/SOIC/TSSOP 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK/IN IN IN IN IN IN IN IN IN IN IN GND VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IN PLCC 5 6 7 8 9 10 11 25 24 23 22 21 20 19 IN IN IN GND * IN IN IN I/O I/O I/O GND * I/O I/O I/O Note: For PLCC, pins 1, 8, 15, and 22 can be left unconnected. For superior performance, connect VCC to pin 1 and GND to pins 8, 15, and 22. |
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