ADF4159CCPZ datasheet(21/36 Pages) AD

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Data Sheet

ADF4159

Rev. E | Page 21 of 36

CLOCK REGISTER (R4) MAP

When Bits DB[2:0] are set to 100, the on-chip clock register

(Register R4) is programmed (see Figure 29).

LE SEL

In some applications, it is necessary to synchronize the LE pin

with the reference signal. To do this, Bit DB31 must be set to 1.

Synchronization is done internally on the part.

Σ-Δ Modulator Mode

To completely disable the Σ-Δ modulator, set Bits DB[30:26] to

0b01110, which puts the ADF4159 into integer-N mode, and

the channel spacing becomes equal to the PFD frequency. Both

the 12-bit MSB fractional value (Register R0, DB[14:3]) and the

13-bit LSB fractional value (Register R1, DB[27:15]) must be set

to 0. After writing to Register 4, Register 3 must be written to twice,

to trigger a counter reset. (That is, write Register 3 with DB3 = 1,

then write Register 3 with DB3 = 0.)

All features driven by the Σ-Δ modulator are disabled, such as

ramping, PSK, FSK, and phase adjust.

Disabling the Σ-Δ modulator also removes the fixed +(fPFD/226)

offset on the VCO output.

For normal operation, set these bits to 0b00000.

Ramp Status

Bits DB[25:21] provide access to the following advanced

features (see Figure 29):

•

Readback to MUXOUT option: the synthesizer frequency

at the moment of interruption can be read back (see the

Interrupt Modes and Frequency Readback section).

•

Ramp complete to MUXOUT option: a logic high pulse

is output on the MUXOUT pin at the end of each ramp.

•

Charge pump up and charge pump down options: the

charge pump is forced to constantly output up or down

pulses, respectively.

When using the readback to MUXOUT or ramp complete

to MUXOUT option, the MUXOUT bits in Register R0

(Bits DB[30:27]) must be set to 1111.

Clock Divider Mode

Bits DB[20:19] are used to enable Ramp Divider mode or Fast

Lock Divider mode. If neither is being used, set these bits to 0b00.

12-Bit CLK2 Divider Value

Bits DB[18:7] program the clock divider (the CLK2 timer) when

the part operates in ramp mode (see the Timeout Interval section).

The CLK2 timer also determines how long the loop remains in

wideband mode when fast lock mode is used (see the Fast Lock

Mode section).

Clock Divider Select

When Bit DB6 is set to 0, CLK2 is used as the CLK2 value for a

standard ramp, such as sawtooth or triangular. When Bit DB6 is

set to 1, CLK2 is used as the CLK2 value for the second ramp of

the Fast Ramp or Dual Ramp functions. For more information,

see the Waveform Deviations and Timing section.

12-BIT CLK2 DIVIDER VALUE

RESERVED

Σ-Δ

MODULATOR MODE

CONTROL

BITS

LS1

D12

D11 D10

D12

D11

...

CLK2 DIVIDER VALUE

...

4092

...

4093

...

4094

...

4095

CLOCK DIVIDER MODE

CLOCK DIVIDER OFF

CS1

CLK

DIV

MODE

LS1

LE SEL

RAMP STATUS

NORMAL OPERATION

CS1

CLK DIV SEL

DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5

DB4

DB3

DB2

DB1

DB0

C3(1) C2(0) C1(0)

READBACK TO MUXOUT

RAMP COMPLETE TO MUXOUT

CHARGE PUMP UP

CHARGE PUMP DOWN

Σ-Δ MODULATOR MODE

NORMAL OPERATION

DISABLED WHEN FRAC = 0

FAST LOCK DIVIDER

RESERVED

RAMP DIVIDER

LE FROM PIN

LE SYNCH WITH REFIN

LOAD CLK DIV 1

LOAD CLK DIV 2

RAMP STATUS

Figure 29. Clock Register (R4) Map

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