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ADF4169CCPZ Datasheet(PDF) 21 Page - Analog Devices

Part # ADF4169CCPZ
Description  Direct Modulation/Fast Waveform Generating, Fractional-N Frequency Synthesizer
PDF  36 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADF4169CCPZ Datasheet(HTML) 21 Page - Analog Devices

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Data Sheet
ADF4169
Rev. 0 | Page 21 of 36
12-BIT CLK2 DIVIDER VALUE
RESERVED
Σ-Δ
MODULATOR MODE
CONTROL
BITS
LS1
S5
S4
S3
S2
S1
R2
R3
R4
R5
R1
R2
R3
R4
R5
R1
C2
C1
D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D12
D11
...
D2
D1
CLK2 DIVIDER VALUE
0
0
...
0
0
0
0
0
...
0
1
1
0
0
...
1
0
2
0
0
...
1
1
3
.
.
...
.
.
.
.
.
...
.
.
.
.
.
...
.
.
.
1
1
...
0
0
4092
1
1
...
0
1
4093
1
1
...
1
0
4094
1
1
...
1
1
4095
C2
C1
CLOCK DIVIDER MODE
0
0
CLOCK DIVIDER OFF
0
1
CS1
0
0
0
CLK
DIV
MODE
1
0
1
1
LS1
LE SEL
0
1
RAMP STATUS
0
NORMAL OPERATION
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
1
0
CS1
CLK DIV SEL
0
1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
DB8
DB7 DB6
DB5
DB4
DB3
DB2
DB1
DB0
C3(1) C2(0) C1(0)
READBACK TO MUXOUT
RAMP COMPLETE TO MUXOUT
CHARGE PUMP UP
CHARGE PUMP DOWN
S2
S3
S4
S5
S1
Σ-Δ MODULATOR MODE
0
NORMAL OPERATION
1
0
0
0
0
1
0
1
0
DISABLED WHEN FRAC = 0
FAST LOCK DIVIDER
RESERVED
RAMP DIVIDER
LE FROM PIN
LE SYNCH WITH REFIN
LOAD CLK2 DIV 1
LOAD CLK2 DIV 2
RAMP STATUS
Figure 29. Clock Register (R4) Map



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