VSC6511 datasheet(13/22 Pages) VITESSE

13 / 22 page

Page 13

4/10/00

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6511

Deserializer/Reclocker at 1.485Gb/s

SMPTE-292M Serializer, Deserializer, and

G52311-0, Rev. 2.0

Figure 8: REFCLK Timing Waveforms: All Modes

Table 6: Reference Clock Requirements *

Note: The PLL locks to the rising edge of REFCLK.

Figure 9: RCLK Timing Waveforms*

Table 7: RCLK Performance - Deserializer and Deserializer/Reclocker Mode

Note: The RCLK output from the CRU is 40% high and 60% low by design.

Parameters

Description

Min

Max

Units

Conditions

Frequency Range

73.75

74.50

MHz

Will accept both 74.176/74.25MHz

Frequency Offset

-1000

1000

ppm.

Difference in REFCLK frequencies

between the transmitting and

receiving VSC6511s.

REFCLK duty cycle

-15

+15

Measured at 1.5V

TH, TL

REFCLK high/low times

3.0

—ns.

Measured between VIL(MAX) to

VIL(MAX) or VIH(MIN) to VIH(MIN)

REFCLK rise

—2.0

ns.

Between VIL(MAX) and VIH(MIN)

Parameters

Description

Min

Max

Units

Conditions

FOFFSET

RCLK Frequency offset from

REFCLK

-1.0

+1.0

Maximum deviation when the CRU is

not locked. Deserializer Mode.

RCLK duty cycle - 40% / 60%

-5

Measured at 1.5V. Deserializer Mode

and Deserializer/Reclocker Mode.

RCLK high times

3—

ns.

Measured between VIH(MIN) to

VIH(MIN)

RCLK low times

5.9

—

ns.

Measured between VIL(MAX) to

VIL(MAX)

RCLK rise/fall time

—1.5

ns.

Between VIL(MAX) and VIH(MIN)

REFCLK

VIL(MAX)

VIH(MIN)

RCLK

VIL(MAX)

VIH(MIN)

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