IXYS

10

IXS839 / IXS839A / IXS839B

Theory of Operation

The IXS839/839A/839B are dual MOSFET drivers,

designed to drive two external N-channel power

MOSFETs. The low-side driver is designed to drive

a non-floating N-channel power MOSFET and its

output is out of phase with the PWM input. The

high-side driver is designed to drive a floating N-

channel power MOSFET and its output is in phase

with the PWM input. An external bootstrap circuit

provides the floating power supply to the high-side

driver.

The bootstrap circuit consists of a Schottky diode

and a boost capacitor. When the PWM input

transitions to a logic low, the low-side power

MOSFET turns ON, the SW node is pulled to

ground, and the bootstrap capacitor is charged to

VDD through the Schottky diode. When the PWM

transitions to a logic high, the high side power

MOSFET begins to turn on and the SW node rises

up to the input supply, VIN. In turn the boost

capacitor raises the BST node voltage to a level

equal to the input supply plus the boost capacitor

voltage, providing sufficient voltage to the BST

node to turn on the High-Side Power MOSFET. An

internal

cross-conduction

prevention

circuit

monitors both gate driver outputs and allows each

driver output to turn ON only when the other output

driver turns OFF and falls below 1V.

The

IXS839A

is

a

cost

reduced

Driver,

differentiated by the absence of the undervoltage

lockout protection circuit featured in the IXS839 and

IXS839B. IXS839A/B must be enabled using the

SD terminal when the driver supply reaches the

operating range. SD can be used to turn off both

driver outputs to prevent the rapid discharge of the

buck converter output capacitors. An additional

terminal, LSD can be used to turn off the Low-Side

Gate Driver Output. The High-Side Gate Driver

remains active in this mode.

Detailed Circuit Description

(Refer to the Application Diagrams)

The PMW input signal controls both the High Side

and Low Side power MOSFET drivers. The Power

MOSFETs are driven so that the SW node follows

the polarity of the PWM signal.

Low-Side Gate Driver

The Low-Side Gate Driver is designed to drive a

ground referenced N-Channel Power MOSFET. In

a synchronous buck converter application, it drives

the gate of the synchronous rectifier FET, (Q2).

When

the

driver

is

enabled,

(IXS839A/B

SD=LSD=VDD), the driver output is 180˚ out of

phase with the PWM input. The internal overlap

protection circuit monitors the High-Side Gate

Driver, and allows the Low-Side Gate Driver to turn

on only when the High-Side Gate Driver output falls

below 1.0 Volt. The supply rails for the Low-Side

Gate Driver are VDD and PGND.

High-Side Gate Driver

The High-Side Gate Driver is designed to drive a

floating N-Channel Power MOSFET referenced to

SW. In a synchronous buck converter application, it

drives the gate of the high side power MOSFET,

(Q1).

When the driver is enabled (IXS839A/B

SD=VDD), the driver output is in phase with the

PWM input. The bootstrap supply rails for the High-

Side Gate Driver are BST and SW, and are

generated by an external bootstrap circuit. The

bootstrap circuit consists of a Schottky diode

DBST, and a bootstrap capacitor CBST. During

start up, the SW pin is at ground and the bootstrap

capacitor CBST charges up to VDD through the

Schottky diode DBST. When the PWM input

transitions high the High-Side Gate Driver begins to

turn Q1 ON by transferring charge from the

bootstrap capacitor CBST to the gate of Q1. As Q1

turns on the SW pin will rise up to VIN, forcing the

BST pin to VIN + VBOOSTCAP. This supplies the

required gate to source voltage to Q1. When PWM

transitions low the High-Side Driver and in turn Q1

switch off. When SW falls below 1 Volt the Low-

Side Gate Driver turns on and recharges the

bootstrap capacitor which completes the cycle.

Overlap Protection Circuit

The overlap protection circuit (OPC) monitors the

High Side and Low Side Gate Driver Outputs and

prevents both main power switches, Q1 and Q2,

from being ON at the same time. This inhibits

excessive shoot-through currents and minimizes

the associated losses.

When the PWM input transitions low, Q1 begins to

turn OFF, and Q2 turns ON only when the High-

Side Gate Driver output falls below 1 volt. By