AD5721 datasheet(16/31 Pages) AD

16 / 31 page

AD5761/AD5721

Data Sheet

Rev. C | Page 16 of 31

–0.01

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

–2

–1

TIME (µs)

SYNC

500-CODE STEP, ±5V SPAN

VDD = +21V

VSS = –11V

TA = 25°C

LOAD = 2kΩ||200pF

Figure 43. 500-Code Step Settling Time, ±5 V Range

–2

–1

TIME (µs)

–0.01

0.01

0.02

0.03

0.04

0.05

0.06

0.07

0.08

0.09

0.10

0.11

0.12

0.13

0.14

0.15

0.16

0.17

0.18

0.19

0.20

VDD = +21V

VSS = –11V

TA = 25°C

LOAD = 2kΩ||200pF

SYNC

500-CODE STEP, ±10V SPAN

Figure 44. 500-Code Step Settling Time, ±10 V Range

–12

–10

–8

–6

–4

–2

–5

TIME (µs)

0nF

1nF

5nF

7nF

10nF

VDD =+21V

VSS = –11V

TA = 25°C

LOAD = 2kΩ

Figure 45. Settling Time vs. Capacitive Load, ±10 V Range

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

–3 –2 –1

10 11 12 13 14 15

TIME (µs)

0nF

1nF

5nF

7nF

10nF

VDD = +21V

VSS = –11V

TA = 25°C

LOAD = 2kΩ

Figure 46. Settling Time vs. Capacitive Load, 0 V to 5 V Range

–0.010

–0.009

–0.008

–0.007

–0.006

–0.005

–0.004

–0.003

–0.002

–0.001

0.001

0.002

0.003

0.004

0.005

0.5

1.0

1.5

2.0

2.5

3.0

3.5

TIME (µs)

VDD = +21V

VSS = –11V

LOAD = 2k

Ω||200pF

TA = 25°C

Figure 47. Digital-to-Analog Glitch Energy, 0 V to 5 V Range

0.5

1.0

1.5

2.0

2.5

3.0

3.5

TIME (µs)

–0.010

–0.008

–0.006

–0.004

–0.002

0.002

0.004

VDD = +21V

VSS = –11V

LOAD = 2k

Ω||200pF

TA = 25°C

Figure 48. Digital-to-Analog Glitch Energy, ±10 V Range

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