LTC2662 datasheet(11/28 Pages) AD

11 / 28 page

LTC2662

Rev 0

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PIN FUNCTIONS

GND (Pins 1, 8, 14, 32): Ground. These pins and the

exposed pad (pin 33) must be tied directly to a solid

ground plane.

TGP (Pin 2): Asynchronous Toggle Pin. A falling edge

updates the DAC register with data from input register

A. A rising edge updates the DAC register with data from

input register B. Toggle operations only affect those DAC

channels with their toggle select bit (Tx) set to 1. Tie

the TGP pin to IOVCC if toggle operations are to be done

through software. Tie the TGP pin to GND if not using

toggle operations. Logic levels are determined by IOVCC.

SDI (Pin 3): Serial Data Input. Data on SDI is clocked into

the DAC on the rising edge of SCK. The LTC2662 accepts

input word lengths of either 24 or 32 bits. Logic levels are

determined by IOVCC.

SDO (Pin 4): Serial Data Output. The serial output of the

32-bit shift register appears at the SDO pin. The data

transferred to the device via the SDI pin is delayed 32

SCK rising edges before being output at the next falling

edge. Can be used for data echo readback or daisy-chain

operation. The SDO pin becomes high impedance when

CS/LD is high. Logic levels are determined by IOVCC.

SCK (Pin 5): Serial Clock Input. Logic levels are deter-

mined by IOVCC.

CS/LD (Pin 6): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting SDI data

into the register. In addition, SDO is enabled when CS/

LD is low. When CS/LD is taken high, SDO and SCK are

disabled and the specified command (see Table 1) is

executed. Logic levels are determined by IOVCC.

LDAC (Pin 7): Active Low Asynchronous DAC Update Pin.

This pin allows updates independent of SPI timing. If

CS/LD is high, a falling edge on LDAC updates all DAC

registers with the contents of the input registers. LDAC is

gated by CS/LD and has no effect if CS/LD is low. Logic

levels are determined by IOVCC.

If not used, tie LDAC to IOVCC.

REFLO (Pin 9): Reference Low. Signal ground for the ref-

erence. Tie directly to GND.

REF (Pin 10): Reference Input/Output. The voltage at the

REF pin proportionally scales the full-scale output current

of each DAC output channel. By default, the internal 1.25V

reference is routed to this pin. This pin must be buffered

when driving external DC load currents. If the reference is

disabled (see Reference Modes in the Operation section),

its output is disconnected and the REF pin becomes a

high impedance input which will accept a precision exter-

nal reference. For low noise and reference stability, tie a

capacitor from this pin to GND. The value must be less

than CREFCOMP, where CREFCOMP is the capacitance tied to

the REFCOMP pin. The allowable external reference input

range is 1.225V to 1.275V.

REFCOMP (Pin 11): Internal Reference Compensation Pin.

For low noise and reference stability, tie a 0.1µF capacitor

from this pin to GND. Tying REFCOMP to GND causes

the part to power up with the internal reference disabled,

allowing the use of an external reference at start-up.

FSADJ (Pin 12): Full-Scale current Adjust pin. This pin

can be used in one of two ways to produce either nomi-

nal, internally-calibrated output ranges, or incrementally-

tunable ranges. In either case, the reference voltage VREF

is forced across a resistor RFSADJ to define a reference

current that scales the outputs for all ranges and chan-

nels. Full-scale currents are proportional to the voltage at

REF (pin 10) and inversely proportional to RFSADJ.

If FSADJ is tied to VCC, an internal RFSADJ (20k) is selected,

resulting in nominal output ranges. An external resistor

of 19k to 41k can be used instead by simply connect-

ing the resistor between FSADJ and GND. In this case

the external resistor controls the scaling of ranges, and

the internal resistor is automatically disconnected. See

Table 3 for details.

When using an external resistor, FSADJ is sensitive to

stray capacitance; the pin should be compensated with

a snubber network consisting of a series combination of

1k and 1µF, connected in parallel to RFSADJ. With the rec-

ommended compensation, the pin is stable driving stray

capacitance of up to 50pF.

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