2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer
CY29942
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07284 Rev. *B
Revised December 21, 2002
42
Features
• 200-MHz clock support
• 2.5V or 3.3V operation
• LVCMOS/LVTTL clock input
• LVCMOS-/LVTTL-compatible inputs
• 18 clock outputs: drive up to 36 clock lines
• 200 ps max. output-to-output skew
• Output Enable control
• Pin compatible with MPC942C
• Available in Industrial and Commercial
• 32-pin LQFP package
Description
The CY29942 is a low-voltage 200-MHz clock distribution buff-
er with an LVCMOS or LVTTL compatible input clock. All other
control inputs are LVCMOS/LVTTL compatible. The eighteen
outputs are 2.5V or 3.3V LVCMOS or LVTTL compatible and
can drive 50
Ω series or parallel terminated transmission lines.
For series terminated transmission lines, each output can
drive one or two traces giving the devices an effective fanout
of 1:36. Low output-to-output skews make the CY29942 an
ideal clock distribution buffer for nested clock trees in the most
demanding of synchronous systems.
Block Diagram
Pin Configuration
TCLK
OE
VDD
18
Q0-Q17
CY29942
Q6
Q7
Q8
VDD
Q9
Q10
Q11
VSS
VSS
VSS
TCLK
NC
OE
NC
VDD
VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
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