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P89LPC9103 Datasheet(PDF) 2 Page - NXP Semiconductors

Part # P89LPC9103
Description  8-bit microcontrollers with two-clock accelerated 80C51 core 1 kB 3 V byte-erasable Flash with 8-bit A/D converter
PDF  58 Pages
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Manufacturer  PHILIPS [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo PHILIPS - NXP Semiconductors

P89LPC9103 Datasheet(HTML) 2 Page - NXP Semiconductors

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9397 750 14655
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 11 April 2005
2 of 58
Philips Semiconductors
P89LPC9102/9103/9107
8-bit microcontrollers with two-clock accelerated 80C51 core
s In-Application Programming (IAP-Lite) and byte erase allows code memory to be used
for non-volatile data storage.
s Serial Flash ICP allows simple production coding with commercial EPROM
programmers. Flash security bits prevent reading of sensitive application programs.
s Watchdog timer with separate on-chip oscillator, requiring no external components.
The watchdog prescaler is selectable from eight values.
s Low voltage reset (Brownout detect) allows a graceful system shutdown when power
fails. May optionally be configured as an interrupt.
s Idle mode and two different reduced power Power-down modes. Improved wake-up
from Power-down mode (a LOW interrupt input starts execution). Typical Power-down
mode current is less than 1
µA (total Power-down mode with voltage comparators
disabled).
s Active-LOW reset. On-chip power-on reset allows operation without external reset
components. A reset counter and reset glitch suppression circuitry prevent spurious
and incomplete resets. A software reset function is also available.
s Programmable port output configuration options: quasi-bidirectional, open drain,
push-pull, input-only.
s Port ‘input pattern match’ detect. Port 0 may generate an interrupt when the value of
the pins match or do not match a programmable pattern.
s LED drive capability (20 mA) on all port pins. A maximum limit is specified for the
entire chip.
s Controlled slew rate port outputs to reduce EMI. Outputs have approximately 10 ns
minimum ramp times.
s Only power and ground connections are required to operate the
P89LPC9102/9103/9107 when internal reset option is selected.
s Four interrupt priority levels.
s Two keypad interrupt inputs.
s Second data pointer.
s External clock input.
s Clock output (P89LPC9102/9107).
s Schmitt trigger port inputs.
s Emulation support.
3.
Product comparison overview
Table 1 highlights the differences between these two devices. For a complete list of device
features, please see Section 2 “Features”.
Table 1:
Product comparison overview
Type number
UART
T0 toggle/PWM
T1 toggle/PWM
CLKOUT
P89LPC9102
-
X
X
X
P89LPC9103
X
-
-
-
P89LPC9107
XXXX



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