AP65355FN-7 datasheet(10/15 Pages) DIODES

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AP65355

Document number: DS37875 Rev. 2 - 2

10 of 15

www.diodes.com

May 2017

AP65355

Application Information (Cont.)

Soft-Start

The soft-start time of the AP65355 is programmable by selecting different CSS values. When the EN pin becomes high, the CSS is charged by a

current source, generating a ramp signal fed into non-inverting input of the error comparator. Reference voltage VREF, or the internal soft-start

voltage SS, (whichever is smaller), dominates the behavior of the non-inverting inputs of the error amplifier. Accordingly, the output voltage will

follow the SS signal and ramp up smoothly to its target level. The capacitor value required for a given soft-start ramp time can be expressed as:





Where CSS is the required capacitor between SS pin and PGND, tSS is the desired soft-start time.

Over Current Protection (OCP)

Figure 4 shows the over current protection (OCP) scheme of AP65355. In each switching cycle, the inductor current is sensed by monitoring the

low-side MOSFET during the OFF period. When the voltage between PGND pin and SW pin is lower than the over current trip level, VLIMIT, the

OCP will be triggered and the controller keeps the OFF state. A new switching cycle will begin when the measured voltage is higher than limit

voltage. After 6µs, the internal OCL (Over Current Logic) threshold is set to a lower level and SS pin is discharged such that output is 0V. Then

the switching action is blanked out for one tSS before soft start re-initiated and OCP threshold is restored to higher value.

Because the RDS(ON) of MOSFET increases with temperature, VLIMIT has 4ppm/°C temperature coefficient to compensate this temperature

dependency of RDS(ON).

COMPARATOR

VLIMIT

Figure 4 Overcurrent Protection Scheme

Under Voltage Lockout

The AP65355 provides an undervoltage lockout circuit to prevent it from undefined status during startup. The UVLO circuit shuts down the device

when VIN drops below 3.45V. The UVLO circuit has 320mV hysteresis, which means the device starts up again when VREG rises to 3.75V (non-

latch).

PG Comparator

PG is an open drain output controlled by a comparator connected to the feedback signal. If FB exceeds 90% of the internal reference voltage, PG

will be high impedance. Otherwise, the PG output is connected to PGND.

Thermal shutdown

If the junction temperature of the device reaches the thermal shutdown limit of +150°C, the AP65355 shuts itself off, and both HMOS and LMOS

will be turned off. The output is discharged with the internal transistor. When the junction cools to the required level (+130°C nominal), the device

initiates soft-start as during a normal power-up cycle.

Power Derating Characteristics

To prevent the regulator from exceeding the maximum junction temperature, some thermal analysis is required. The temperature rise is given by:

 







RISE

Where PD is the power dissipated by the regulator and JA is the thermal resistance from the junction of the die to the ambient temperature. The

junction temperature, TJ, is given by:

RISE





TA is the ambient temperature of the environment. The actual junction temperature should not exceed the absolute maximum junction temperature

of +125°C when considering the thermal design.

Setting the Output Voltage

The output voltage can be adjusted from 0.76 using an external resistor divider. Table 1 shows a list of resistor selection for common output

voltages. Resistor R1 is selected based on a design tradeoff between efficiency and output voltage accuracy. For high values of R1 there is less

current consumption in the feedback network. However, the tradeoff is output voltage accuracy due to the bias current in the error amplifier. R1

can be determined by the following equation:



















0.765

OUT

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