GC4016 datasheet(52/83 Pages) TI

52 / 83 page

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August 27, 2001

GC4016 MULTI-STANDARD QUAD DDC CHIP

DATA SHEET REV 1.0

This document contains information which may be changed at any time without notice

ADDRESS 17:

Output Format, Suggested default = 0x40

ADDRESS 18:

Output Mode Cleared on powerup., Suggested default = (see Table 3)

BIT

TYPE

NAME

DESCRIPTION

0 (LSB)

R/W

INV_SCK

Invert SCK output. The serial, nibble, link and parallel outputs normally change

on the rising edge of SCK. If INV_SCK is set high the clock is inverted so data

changes on the falling edge.

R/W

INV_RDY

Invert RDY output. RDY is normally active high. This control bit is used for uP

and parallel modes. It has no effect in serial, LINK, or nibble modes.

R/W

INV_SFS

Invert SFS output. SFS is normally active high.

R/W

TAG_EN

Enable tags. The four bit tags replace the four LSBs of the data when TAG_EN

is set. The BITS_PER_WORD (address 20) control determines the tag location.

R/W

RDY_WIDTH

The RDY pulse is 4 (RDY_WIDTH=0) or 16 (RDY_WIDTH=1) CK cycles. Valid

for the uP mode only, must be set to 0 for all other modes.

5-7 (MSB)

R/W

OUT_BLK_SYNC

Output circuit sync source. See table 7 for the sync modes.

The OUT_BLK_SYNC is used to synchronize the output timing among multiple

GC4016 chips. The OUT_BLK_SYNC should only be made active during

initialization. Use during operation may cause unknown output transients.

BIT

TYPE

NAME

DESCRIPTION

0 (LSB)

R/W

LINK

Enable LINK protocol. This mode supports Analog Devices LINK protocol. In

this mode the RDY pin serves as LINK Acknowledge and is an input to the

GC4016 (EN_RDY must be low). NIBBLE must also be set high (eight bit LINK

mode is not supported) and OUTPUT_MODE must be set to 2. The PARALLEL

control bit must be low.

R/W

NIBBLE

Enable nibble mode. This mode is similar to serial except the four pins P0-3

output one nibble at a time. TDM of several chips is supported with one acting

as the master (EN_RDY=MASTER=1) and the others as the slave

(EN_RDY=MASTER=0).

R/W

PARALLEL

Enable parallel mode.

R/W

MASTER

Normally set high. Is set low by slave chips in TDM serial or nibble modes. The

RDY pin is an output when MASTER=1, and is an input when MASTER=0.

R/W

REAL_ONLY

Normally set low. Is set high when outputting real, instead of complex, data.

Normally used with the complex to real modes of the PFIR (see Section 3.3.7).

5-6

R/W

OUTPUT_MODE

The output mode selection is:

0 for microprocessor mode,

1 for serial mode,

2 for nibble or LINK modes, or

3 for parallel mode.

Note that only one mode is supported at a time.

7 (MSB)

R/W

REVERSE_IQ

Used when OUTPUT_ORDER=0 to swap I and Q. This is useful for link or

nibble mode outputs when packing two 16 bit words into a 32 bit transfer. See

Section 3.8.5.

GC4016 Datasheet(PDF) 52 Page - Texas Instruments

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