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PRELIMINARY

XRT94L43

SONET/SDH STS-12/STM-4 TO E3/DS3/STS-1 MAPPER/DEMAPPER

SEPTEMBER 2001

REV. P1.0.0

GENERAL DESCRIPTION

The XRT94L43 is a highly integrated SONET/SDH

terminator designed for E3/DS3/STS-1 mapping/de-

mapping functions from either the STS-12 or STM-4

data stream. The XRT94L43 interfaces to either STS-

12 or STM-4 signals using a byte wide parallel inter-

face in Telecom Bus format or via serial line interface

that operates at 622.08 MHz.

The XRT94L43 processes the section,line and path

overhead in the SONET/SDH data stream. The pro-

cessing of path overhead bytes within the STS-1s or

TUG-3s includes 64 bytes for storing the J1 bytes.

Path overhead bytes can be accessed through the

microprocessor interface or via serial interface.

The XRT94L43 uses the internal E3/DS3 De-Syn-

chronizer circuit with an internal pointer leak algo-

rithm for clock smoothing as well as to remove the jit-

ter due to mapping and pointer movements. These

De-Synchronizer circuits do not need any external

clock reference for its operation.

The SONET/SDH transmit blocks allow flexible inser-

tion of TOH and POH bytes through both Hardware

and Software. Individual POH bytes for the transmit-

ted SONET/SDH signal are mapped either from the

XRT94L43 memory map or from external interface.

A1,A2 framing pattern, C1 byte and H1,H2 pointer

byte are generated.

The SONET/SDH receive blocks receive SONET

STS-3 signal or SDH STM-1 signal and perform the

necessary transport and path overhead processing.

The XRT94L43 provides a line side APS (Automatic

Protection Switching) interface by offering redundant

receive serial interface to be switched at the frame

boundary.

The XRT94L43 provides 12 mappers for performing

STS-1/VC-3 to STS-1/DS3/E3 mapping function, one

for each STS-1/DS3/E3 framers.

A PRBS test pattern generation and detection is im-

plemented to measure the bit-error performance.

A general purpose microprocessor interface is includ-

ed for control, configuration and monitoring.

FEATURES

• Provides DS3/ E3 mapping/de-mapping for up to 12

tributaries through SONET STS-1 or SDH AU-3

and/or TUG-3/AU-4 containers.

• Generates

and

terminates

SONET/SDH

sec-

tion,line and path layers.

• Integrated SERDES with Clock Recovery Circuit.

• Provides SONET frame scrambling and descram-

bling.

• Integrated Clock Synthesizer that generates 622.08

MHz and 77.76 MHz clock from an external 12.96/

19.44/77.76 MHz reference clock.

• Provides STS-1 (EC1) mapping/de-mapping for up

to 12 STS-1s.

• Integrated 12 E3/DS3/STS-1 De-Synchronizer cir-

cuit that de-jitter gapped clock to meet 0.05UIpp jit-

ter requirements.

• Access to Line or Section DCC

• Level 2 Performance Monitoring for E3 and DS3.

• Supports mixing of STS-1E and DS3 or E3 and

DS3 tributaries.

• Performs STS-3/STM-1 to STS-12/STM-4 Map-

ping/De-Mapping.

• E3 and DS3 framers for both Transmit and Receive

directions.

• Complete Transport/Section Overhead Processing

and generation per Telcordia and ITU standards.

• Complete Path Overhead processing and genera-

tion for one STS-12 or for 12 STS-1s

• Full line APS support for redundancy applications.

• Loopback support for both SONET/SDH as well as

E3/DS3/STS-1.

• Boundary scan capability with JTAG IEEE 1149.1

• 8-bit microprocessor interface

• Power Supply 2.5 V for Core and 3.3 V for I/O

• -40°C to +85°C Operating Temperature Range

• Available in a 516 Ball PBGA package

APPLICATIONS

• Network switches

• Add/Drop Multiplexer

• W-DCS Digital Cross Connect Systems