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MFR4200 Datasheet(PDF) 39 Page - Freescale Semiconductor, Inc

Part # MFR4200
Description  FlexRay Communication Controllers
PDF  260 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MFR4200 Datasheet(HTML) 39 Page - Freescale Semiconductor, Inc

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Signal Descriptions
MFR4200 Data Sheet, Rev. 0
Freescale Semiconductor
39
MT is active, irrespective of which physical layer is selected. If the RS485 driver type is selected, this pin
is not used.
This signal should be connected to the Bus Guardians on each channel. The pin can be configured to
provide either high or reduced output drive.
CLK_S1 is the CLKOUT clock frequency selection input signal. See Table 2-2.
NOTE
CLK_S[0:1] signals are inputs during the internal reset sequence and are
latched by the internal reset signal level.
While the CLK_S1 value is being latched, the output drive control is
disabled and the internal pulldown resistor is connected to the pin.
As CLK_S[0:1] signals share pins with Physical Layer Interface signals,
pullup/down devices must be used for the selection. Recommended
pullup/down resistor values for the CLK_S[0:1] inputs are given in
Section 2.4.2, “Recommended Pullup/down Resistor Values”.
2.2.3.11
ARM/DBG1/CLK_S0 — Bus Guardian ARM, Debug Strobe Point 1, Clock
Output Select 0
ARM is an output signal from the CC to a bus guardian. If a bus guardian device is not used in an
application, this pin may be left open.
ARM is active, irrespective of which physical layer is selected. If the RS485 driver type is selected, this
pin is not used.
This signal should be connected to the bus guardian on each channel. The pin can be configured to provide
either high or reduced output drive.
DBG1 is the debug strobe point output 1. The function output on this pin is selected by the debug port
control register. Refer to Section 3.10, “Debug Port” for more information.
CLK_S0 is the CLKOUT clock frequency selection input signal. See Table 2-2.
NOTE
CLK_S[0:1] signals are inputs during the internal reset sequence and are
latched by the internal reset signal level.
While the CLK_S0 value is being latched, the output drive control is
disabled and the internal pulldown resistor is connected to the pin.
As CLK_S[0:1] signals share pins with Physical Layer Interface signals,
pullup/down devices must be used for selection. Recommended
pullup/down resistor values for the CLK_S[0:1] inputs are given in the
Section 2.4.2, “Recommended Pullup/down Resistor Values”.



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