CS5466

7

DIGITAL CHARACTERISTICS (Note 6)

•

Min / Max characteristics and specifications are guaranteed over all Operating Conditions.

•

Typical characteristics and specifications are measured at nominal supply voltages and TA = 25 °C.

•

VA+ = VD+ = 5V ±5%; AGND = DGND = 0 V. All voltages with respect to 0 V.

•

MCLK = 4.096 MHz

Notes:

6.

All measurements performed under static conditions.

7.

If external MCLK is used, then the duty cycle must be between 45% and 55% to maintain this specification.

8.

The frequency of CPUCLK is equal to MCLK.

9.

Parameter

Symbol

Min

Typ

Max

Unit

Master Clock Characteristics

Master Clock Frequency

Internal Gate Oscillator

MCLK

3

4.096

5

MHz

Master Clock Duty Cycle

40

-

60

%

CPUCLK Duty Cycle

(Note 7 and 8)

40

60

%

Filter Characteristics

High Pass Filter Corner Frequency

-3 dB

-

0.125

-

Hz

Input/Output Characteristics

High-Level Input Voltage

XIN

RESET

(VD+) - 0.5

0.8 VD+

-

-

-

-

V

V

Low-Level Input Voltage (VD = 5 V)

XIN

RESET

-

-

-

-

1.5

0.2 VD+

V

V

Low-Level Input Voltage (VD = 3.3 V)

XIN

RESET

-

-

-

-

0.3

0.2 VD+

V

V

High-Level Output Voltage (except XOUT)

(VD+) - 1.0

-

-

V

Low-Level Output Voltage (except XOUT)

--

0.4

V

Input Leakage Current

-±1

±10

µA

Digital Output Pin Capacitance

-5

-

pF

Drive Current FOUT, E1, E2, NEG

(Note 9)

90

mA