LD5850

9

Leadtrend Technology Corporation

www.leadtrend.com.tw

LD5850-DS-00

November 2012

spikes below 275ns and the negative spike of the CS pin

below -0.5V.

However, the pulse width of the turn-on spike is

determined according to the output power, circuit design

and PCB layout.

It is strongly recommended to add a

smaller R-C filter for large power application to avoid CS

pin from being damaged by the negative turn-on spike.

CS

Removable if the negative

Spike is not over spec (-0.5V)

DRV

275ns

blanking

time

OCP

Signal

0.5V

Fig. 2

V

5

.

3

)

R

I

3

(

)

Duty

3

.

1

(

5

.

1

CS

)

Peak

(

L

(%)













x3

Sense

Amplifier

EA

S

CS

COMP

FB

Thermal Protection

Thermal protection limits the whole power dissipation in

this device. When the junction temperature reaches 150°C

approximately, the thermal sensor will send the signal of

shutdown logic to turn off this device and resume the

operation

after the IC’s junction temperature cools by 30°

C

PCB Layout Guideline

It’s recommended to separate the high frequency

switching current from the low-level control signals in

layout. The high switching current (MOSFET, inductor,

gate driver and FB return ends) may disturb the other

low-level signals in the feedback loop and protection

circuitry. As a result, it may cause the control function to

behave abnormally. To avoid these side effects, a few

guidelines are recommended for the PCB layout as below.

1. Route the VIN bypass capacitor and the signal ground

close to the IC as possible. The traces between

capacitor and VIN pin should be short as possible to

avoid noise interference.

2. Use broader traces for VIN, VOUT and power ground.

Those components connected to VIN, VOUT and

power ground carry high input/output current, such as

power

MOSFET

and

decoupling

capacitors.

To

minimize power loss in these traces, the resistance of

traces should be kept as low as possible.

3. Use broader traces between power MOSFET drain,

inductor and diode since they often carry high current

in these traces. To minimize power loss in these traces,

the resistance of traces should be minimized as

possible.

4. Keep the gate drive traces short and broad around the

IC driver output, DRV pin, and the power MOSFET.

The driving traces have a high current spike during

inverter operation. To minimize power MOSFET

switching loss or oscillation voltage in the gate driver

signal, the drive traces should be as broad and short

as possible to minimize resistance and parasitic

inductance.