HD64F3670 datasheet(13/323 Pages) RENESAS

13 / 323 page

Rev. 2.0, 03/02, Page xi of xxii

11.5.6 Timing of IMFA to IMFD Flag Setting at Compare Match ............................... 147

11.5.7 Timing of IMFA to IMFD Setting at Input Capture .......................................... 148

11.5.8 Timing of Status Flag Clearing ........................................................................ 148

11.6

Usage Notes................................................................................................................. 149

Section 12 Watchdog Timer ...........................................................................151

12.1

Features ....................................................................................................................... 151

12.2

Register Descriptions ................................................................................................... 151

12.2.1 Timer Control/Status Register WD (TCSRWD) ............................................... 152

12.2.2 Timer Counter WD (TCWD) ........................................................................... 153

12.2.3 Timer Mode Register WD (TMWD) ................................................................ 153

12.3

Operation..................................................................................................................... 154

Section 13 Serial Communication Interface3 (SCI3) ......................................155

13.1

Features ....................................................................................................................... 155

13.2

Input/Output Pins ......................................................................................................... 157

13.3

Register Descriptions ................................................................................................... 157

13.3.1 Receive Shift Register (RSR)........................................................................... 158

13.3.2 Receive Data Register (RDR) .......................................................................... 158

13.3.3 Transmit Shift Register (TSR).......................................................................... 158

13.3.4 Transmit Data Register (TDR) ......................................................................... 158

13.3.5 Serial Mode Register (SMR) ............................................................................ 159

13.3.6 Serial Control Register 3 (SCR3) ..................................................................... 160

13.3.7 Serial Status Register (SSR)............................................................................. 162

13.3.8 Bit Rate Register (BRR) .................................................................................. 164

13.4

Operation in Asynchronous Mode ................................................................................ 169

13.4.1 Clock .............................................................................................................. 169

13.4.2 SCI3 Initialization ........................................................................................... 170

13.4.3 Data Transmission ........................................................................................... 171

13.4.4 Serial Data Reception ...................................................................................... 173

13.5

Operation in Clocked Synchronous Mode ..................................................................... 177

13.5.1 Clock .............................................................................................................. 177

13.5.2 SCI3 Initialization ........................................................................................... 177

13.5.3 Serial Data Transmission ................................................................................. 178

13.5.4 Serial Data Reception (Clocked Synchronous Mode)........................................ 180

13.5.5 Simultaneous Serial Data Transmission and Reception ..................................... 182

13.6

Multiprocessor Communication Function ..................................................................... 184

13.6.1 Multiprocessor Serial Data Transmission ......................................................... 186

13.6.2 Multiprocessor Serial Data Reception .............................................................. 187

13.7

Interrupts ..................................................................................................................... 191

13.8

Usage Notes................................................................................................................. 192

13.8.1 Break Detection and Processing ....................................................................... 192

13.8.2 Mark State and Break Sending ......................................................................... 192

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