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PI6C671F Datasheet(PDF) 4 Page - Pericom Semiconductor Corporation

Part # PI6C671F
Description  Clock Generator for Pentium Modules
PDF  7 Pages
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Manufacturer  PERICOM [Pericom Semiconductor Corporation]
Direct Link  http://www.pericom.com
Logo PERICOM - Pericom Semiconductor Corporation

PI6C671F Datasheet(HTML) 4 Page - Pericom Semiconductor Corporation

  PI6C671F Datasheet HTML 1Page - Pericom Semiconductor Corporation PI6C671F Datasheet HTML 2Page - Pericom Semiconductor Corporation PI6C671F Datasheet HTML 3Page - Pericom Semiconductor Corporation PI6C671F Datasheet HTML 4Page - Pericom Semiconductor Corporation PI6C671F Datasheet HTML 5Page - Pericom Semiconductor Corporation PI6C671F Datasheet HTML 6Page - Pericom Semiconductor Corporation PI6C671F Datasheet HTML 7Page - Pericom Semiconductor Corporation  
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PS8137A
03/15/99
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI6C671F
Clock Generator for Pentium Modules
Byte 1: CPU 24/48 MHz Active/Inactive Register
(1 = enable, 0 = disable)
t
i
B.
o
N
n
i
Pp
u
r
e
w
o
P
@n
o
i
t
p
i
r
c
s
e
D
73
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
z
H
M
4
2
/
8
4
62
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
z
H
M
4
2
/
8
4
5X
)
d
e
v
r
e
s
e
R
(
4A
/
NX
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
K
L
C
U
P
C
38
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
K
L
C
U
P
C
29
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
K
L
C
U
P
C
11
41
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
K
L
C
U
P
C
02
41
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
K
L
C
U
P
C
Byte3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
t
i
B.
o
N
n
i
Pp
u
r
e
w
o
P
@n
o
i
t
p
i
r
c
s
e
D
76
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
7
M
A
R
D
S
67
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
6
M
A
R
D
S
59
21
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
M
A
R
D
S
40
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
M
A
R
D
S
32
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
M
A
R
D
S
23
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
M
A
R
D
S
15
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
M
A
R
D
S
06
31
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
M
A
R
D
S
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
t
i
B.
o
N
n
i
Pp
u
r
e
w
o
P
@n
o
i
t
p
i
r
c
s
e
D
7X
)
d
e
v
r
e
s
e
R
(
68
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
F
_
K
L
C
I
C
P
56
11
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
K
L
C
I
C
P
44
11
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
K
L
C
I
C
P
33
11
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
K
L
C
I
C
P
22
11
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
K
L
C
I
C
P
11
11
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
K
L
C
I
C
P
09
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
K
L
C
I
C
P
Byte 4: SDRAMActive/Inactive Register
(1 = enable, 0 = disable)
t
i
B.
o
N
n
i
Pn
o
i
t
p
i
r
c
s
e
D
7A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
5
1
M
A
R
D
S
6A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
4
1
M
A
R
D
S
5A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
3
1
M
A
R
D
S
4A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
1
M
A
R
D
S
3A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
1
M
A
R
D
S
2A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
1
M
A
R
D
S
1A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
9
M
A
R
D
S
0A
/
N)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
8
M
A
R
D
S
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
t
i
B.
o
N
n
i
Pp
u
r
e
w
o
P
@n
o
i
t
p
i
r
c
s
e
D
7X
)
d
e
v
r
e
s
e
R
(
6X
)
d
e
v
r
e
s
e
R
(
51
)
d
e
v
r
e
s
e
R
(
45
41
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
C
I
P
A
O
I
3X
)
d
e
v
r
e
s
e
R
(
27
41
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
2
F
E
R
11
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
1
F
E
R
02
1
)
e
v
i
t
c
a
n
I
/
e
v
i
t
c
A
(
0
F
E
R
Byte 6: Optional Register
for Possible Future Requirements
t
i
Br
e
b
m
u
N
n
i
Pn
o
i
t
p
i
r
c
s
e
D
7X
)
d
e
v
r
e
s
e
R
(
6X
)
d
e
v
r
e
s
e
R
(
5X
)
d
e
v
r
e
s
e
R
(
4X
)
d
e
v
r
e
s
e
R
(
3X
)
d
e
v
r
e
s
e
R
(
2X
)
d
e
v
r
e
s
e
R
(
1X
)
d
e
v
r
e
s
e
R
(
0X
)
d
e
v
r
e
s
e
R
(



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