DS1743/DS1743P

Y2KC Nonvolatile Timekeeping RAM

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DESCRIPTION

The DS1743 is a full function, year 2000-compliant (Y2KC), real-time clock/calendar (RTC) and 8k x 8 non-volatile static RAM.

User access to all registers within the DS1743 is accomplished with a bytewide interface as shown in Figure 1. The Real Time

Clock (RTC) information and control bits reside in the eight uppermost RAM locations. The RTC registers contain century, year,

month, date, day, hours, minutes, and seconds data in 24-hour BCD format. Corrections for the day of the month and leap year

are made automatically. The RTC clock registers are double buffered to avoid access of incorrect data that can occur during clock

update cycles. The double buffered system also prevents time loss as the timekeeping countdown continues unabated by access

to time register data. The DS1743 also contains its own power-fail circuitry, which deselects the device when the Vcc supply is in

an out of tolerance condition. This feature prevents loss of data from unpredictable system operation brought on by low Vcc as

errant access and update cycles are avoided.

PACKAGES

The DS1743 is available in two packages (28-pin DIP and 34-pin PowerCap module). The 28-pin DIP style module integrates the

crystal, lithium energy source, and silicon all in one package. The 34-pin PowerCap Module Board is designed with contacts for

connection to a separate PowerCap (DS9034PCX) that contains the crystal and battery. This design allows the PowerCap to be

mounted on top of the DS1743P after the completion of the surface mount process. Mounting the PowerCap after the surface

mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. The PowerCap

is keyed to prevent reverse insertion. The PowerCap Module Board and PowerCap are ordered separately and shipped in

separate containers. The part number for the PowerCap is DS9034PCX.

CLOCK OPERATIONS-READING THE CLOCK

While the double buffered register structure reduces the chance of reading incorrect data, internal updates to

the DS1743 clock registers should be halted before clock data is read to prevent reading of data in transition.

However, halting the internal clock register updating process does not affect clock accuracy. Updating is halted

when a 1 is written into the read bit, bit 6 of the century register, see Table 2. As long as a 1 remains in that

position, updating is halted. After a halt is issued, the registers reflect the count,that is day, date, and time that

was current at the moment the halt command was issued. However, the internal clock registers of the

double-buffered system continue to update so that the clock accuracy is not affected by the access of data. All

of the DS1743 registers are updated simultaneously after the internal clock register updating process has been

re-enabled. Updating is within a second after the read bit is written to 0.

DS1743 BLOCK DIAGRAM Figure 1