MSM7650 datasheet(18/34 Pages) OKI

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¡ Semiconductor

MSM7650

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CLOCK TIMING

Input Data Timing

Input data and sync signals are fed into the encoder at the rising edge of the clock.

Input data is handled as valid pixel data when tSTART passes after the falling edge of HSYNC_L.

Chrominance signal of input data at this time is regarded as Cb.

don't care

YD, CD

OLC, OLR

OLG, OLB

HSYNC_L

CLKX1

BLANK_L

tSTART

tACT

ts1

th1

VALID DATA

ACTIVE VIDEO LINE

Video data input timing

Input data is recognized as valid pixel data when input signal BLANK_L is high in the tACT

period.

When BLANK_L is high during the blanking period, however, input data is not output as valid

pixel data since processing to maintain blanking period is internally in-progress.

The values of tSTART differ slightly in master mode and slave mode. The values of tSTART are as

follows.

Operation mode

CCIR 601 NTSC

Square Pixel NTSC

4Fsc NTSC

CCIR PAL

Square Pixel PAL

In master mode

tSTA(Ts)

126

141

115

134

154

Operation mode

CCIR 601 NTSC

Square Pixel NTSC

4Fsc NTSC

CCIR PAL

Square Pixel PAL

In slave mode

tSTA(Ts)

129

144

118

137

157

tSTA–tS1=tSTART

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