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SF5565MLGT Datasheet(PDF) 2 Page - SIFIRST TECHNOLOGIES NANHAI LIMITED |
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SF5565MLGT Datasheet(HTML) 2 Page - SIFIRST TECHNOLOGIES NANHAI LIMITED |
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2 / 2 page ![]() ©SiFirst Technology - 2 - Confidential SiFirst_DS_5565M_V1.0 SF5565M Pin Configuration GND FB 1 2 3 6 5 4 BO GATE VDD CS SOT23-6 Ordering Information Part Number Top Mark Package Tape & Reel SF5565MLGT 65MYW SOT26 Green Yes Marking Information 65M YW Dot: Pin1 Mark 65M:Part number SF5565M YW: Year&Week Code Pin Description Pin Num Pin Name I/O Description 1 GND P Ground 2 FB I Voltage feedback pin. The loop regulation is achieved by connecting a photo-coupler to this pin. PWM duty cycle is determined by this pin voltage and the current sense signal at Pin 4. 3 BO I Brownout protection detection pin. Connect a resistor divider between this pin and bulk capacitor voltage to set the brownout level. If the voltage is below threshold voltage, the PWM output will be disabled. 4 CS I Current sense input pin. 5 VDD P IC power supply pin. 6 GATE O Totem-pole gate driver output to drive the external MOSFET. |
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