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ICS91309 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS91309 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 9 page  Integrated Circuit Systems, Inc. General Description Features ICS91309 0093G—02/11/04 Block Diagram High Performance Communication Buffer Pin Configuration • Zero input - output delay • Frequency range 10 - 133 MHz (3.3V) • 5V tolerant input REF • High loop filter bandwidth ideal for Spread Spectrum applications. • Less than 125 ps cycle to cycle Jitter • Skew controlled outputs • Available in 16 pin, 150 mil SSOP, SOIC & 4.40mm TSSOP packages • Skew: Group-to-Group: <215 ps • Skew within Group: <100 ps • Commercial temperature range: 0°C to +70°C The ICS91309 is a high performance, low skew, low jitter zero delay buffer. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. The ICS91309 provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer. ICS91309 has two banks of four outputs controlled by two address lines. Depending on the selected address line, bank B or both banks can be put in a tri-state mode. In this mode, the PLL is still running and only the output buffers are put in a high impedance mode. The test mode shuts off the PLL and connects the input directly to the output buffers (see table below for functionality). ICS91309 comes in a 16-pin 150 mil SOIC, SSOP or 4.40mm TSSOP package. In the absence of REF input, the device will enter a powerdown mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition. 16 pin SSOP, SOIC & TSSOP REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 FS2 CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 FS1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 Functionality FS2 FS1 CLKA(1:4) CLKB(1:4) CLKOUT Ouput Source PLL Shutdown 0 0 Tristate Tristate Driven PLL N 0 1 Driven Tristate Driven PLL N 10 PLL Bypass Mode PLL Bypass Mode PLL Bypass Mode REF Y 1 1 Driven Driven Driven PLL N |
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