GPCE2048A datasheet(8/24 Pages) GENERALPLUS

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GPCE2048A

Proprietary & Confidential

Jun 02, 2016

Version: 1.2

6 FUNCTION DESCRIPTIONS

6.1 CPU

The

GPCE2048A

equipped

with

16-bit

’nSP™

microprocessor developed by Sunplus.

Eight registers are

involved in

’nSP™: R1 - R4 (General-purpose registers), PC

(Program Counter), SP (Stack Pointer), Base Pointer (BP) and

SR (Segment Register).

The interrupts include three FIQs (Fast

Interrupt Request) and eight IRQs (Interrupt Request), plus one

software-interrupt, BREAK.

6.2 Memory

6.2.1 SRAM

The amount of SRAM is 2K-word (including Stack), ranged from

$0000 through $07FF with access speed of two CPU clock

cycles.

Fosc/n

n:1,2,4,8,16,32,64

b2 b1 b0

of P_SystemClock(W)($2030H)

CPU clock frequency selection

CPU Clock

32768Hz X'tal

b7,b6,b5 of P_SystemClock(W)($2030H)

System clock frequency selection

(Default : Fosc/8)

Phase Lock Loop

(PLL)

System Clock generator

PLL OUT

FOSC

24.576MHz(default)

20.48MHz

32.768MHz

40.96MHz

49.152MHz

6.2.2 ROM

GPCE2048A features a 24K-word high-speed memory with

access speed of two CPU clock cycles.

6.3 PLL, Clock, Power Mode

6.3.1 PLL (Phase Lock Loop)

The purpose of PLL is to provide a base frequency (32768Hz)

and to pump the frequency from 20.48MHz to 49.152MHz for

system clock (FOSC).

The default PLL frequency is 24.576MHz.

6.3.1.1

System clock

Basically, the system clock is provided by PLL and programmed

by the Port_SystemClock (R/W) to determine the clock frequency

for system.

The default system clock FOSC = 24.576MHz and

CPU clock is FOSC/8 if not specified.

The initial CPU clock is

Fosc/8 after system wakes up and adjusts to desired CPU clock

via programming the Port_SystemClock (R/W).

This avoids

ROM reading failure when system awakes.

6.3.1.2

32768Hz RTC

The Real Time Clock (RTC) is normally used in watch, clock or

other time related products.

A 2Hz-RTC (0.5 seconds) function

is loaded in GPCE2048A.

The RTC counts the time as well as

to wake CPU up whenever RTC occurs.

Since the RTC is

generated each 0.5 seconds, time can be traced by the number

of RTC occurrences.

In addition, GPCE2048A supports

32768Hz crystal oscillator in normal mode and auto-power-saving

mode.

In normal mode, 32768Hz OSC always runs at the

highest power consumption.

In auto-power-saving mode,

however, it runs at normal mode for the first 7.5 seconds and

switches back to power-saving mode automatically to save

powers.

6.4 Standby Mode

The GPCE2048A features a power savings mode (or called

standby mode) for low power applications.

To enter standby

mode, the desired key wakeup port (IOA[15:0]) must be

configured to input first.

And read the Port_IOA_Data to latch

the IOA state before entering the standby mode.

Also

remember to enable the corresponding interrupt source(s) for

wakeup.

After that, stop the CPU clock by writing $5555 into

Port_System_Sleep(W) to enter standby mode.

In such mode,

SRAM and I/Os remain in the previous states until CPU being

awakened.

The wakeup sources in GPCE2048A include KEY

wakeup (IOA[15:0]), RTC wakeup, FIQ and IRQ0 - IRQ7.

After

GPCE2048A is awakened, CPU will continue to execute the

program from where it slept.

Programmer can also enable or

disable the 32768Hz RTC when CPU is in standby mode.

GPCE2048A Datasheet(PDF) 8 Page - Generalplus Technology Inc.

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