GPCL A1/B1 Series

© Generalplus Technology Inc.

Proprietary & Confidential

14

Sep. 15, 2015

Version: 1.0

9. APPLICATION CIRCUITS

9.1. Light Loading And Circuit without Noise

PCB Layout Guidelines :

1. R1 should be as close as possible to ROSC pin.

2. C3 should be as close as possible to AVDD/AVSS, and C3 can be removed if there is good power line layout on PCB that

no harm to sound quality.

3. L1 should be as close as possible to VIN/Lpump. Please use inductor with lower resistance to gain higher efficiency.

22uH/0.5W@IDC(max)>250mA ,DCR<1.5ohm is the suggested inductance spec. .

4. The value of C2 depends on the loading. 10uF~47uF is the suggested value range. One end of C2 should be placed

between VSS and VSSIN. The other end of C2 should be placed between VDDO and VDD. C2 should be as close as

possible to VDDO/VDD .

5. Please use capacitor (C2) with low resistance to reduce noise , ESR<2 ohm in 0~70C is suggested.

RESETB

AUDP

AUDN

VIN

VSSIN

13-10

9 - 2

(Battery Power)

(DC-DC Ground)

22

1

VSS

18

20

25

IOC[3:0]

IOC[3:0]

IOD[7:0]

IOD[7:0]

ROSC

15

10~47uF

21

Lpump

22uH

0.1uF

VDD

(Core Power)

VSS

(Core Ground)

(Battery)

19

23

24

17

16

C5

0.1uF

GPCL A1/B1

Series