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NT5CB128M8FN Datasheet(PDF) 96 Page - Nanya Technology Corporation. |
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NT5CB128M8FN Datasheet(HTML) 96 Page - Nanya Technology Corporation. |
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96 / 165 page ![]() DDR3(L) 1Gb SDRAM NT5CB(C)128M8FN / NT5CB(C)64M16FP(Y) Version 1.8 96 Nanya Technology Cooperation © 08/ 2015 All Rights Reserved. DDR3 Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - ) Symbol Parameter DDR3-800, 1066, 1333, & 1600 Unit Notes Min Max VIHdiff Differential input high + 0.200 Note 3 V 1 VILdiff Differential input logic low Note 3 - 0.200 V 1 VIHdiff(ac) Differential input high ac 2 x (VIH(ac) - Vref) Note 3 V 2 VILdiff(ac) Differential input low ac Note 3 2 x (VIL(ac) - Vref) V 2 NOTE 1. Used to define a differential signal slew-rate. NOTE 2. For CK - use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU ,U use VIH/VIL(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group,then the reduced level applies also here. NOTE 3. These values are not defined; however, the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications” DDR3L Differential AC and DC Input Levels for clock (CK - ) and strobe (DQS - ) Symbol Parameter DDR3L-800, 1066, 1333, 1600 & 1866 Unit Notes Min Max VIHdiff Differential input high + 0.180 Note 3 V 1 VILdiff Differential input logic low Note 3 - 0.180 V 1 VIHdiff(ac) Differential input high ac 2 x (VIH(ac) - Vref) Note 3 V 2 VILdiff(ac) Differential input low ac Note 3 2 x (VIL(ac) - Vref) V 2 NOTE 1 Used to define a differential signal slew-rate. NOTE 2 For CK - use VIH/VIL(AC) of ADD/CMD and VREFCA; for DQS - , DQSL, L, DQSU , U use VIH/VIL(AC) of DQs and VREFDQ; if a reduced AC-high or AC-low level is used for a signal group, then the reduced level applies also here. NOTE 3 These values are not defined, however the single-ended signals CK, , DQS, , DQSL, L, DQSU, U need to be within the respective limits (VIH(DC) max, VIL(DC)min) for single-ended signals as well as the limitations for overshoot and undershoot. Refer to “Overshoot and Undershoot Specifications”. |
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