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NT5CC128M8FN-DII Datasheet(PDF) 18 Page - Nanya Technology Corporation.

Part # NT5CC128M8FN-DII
Description  Commercial, Industrial and Automotive DDR3(L) 1Gb SDRAM
PDF  165 Pages
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Manufacturer  NANYA [Nanya Technology Corporation.]
Direct Link  http://www.nanya.com
Logo NANYA - Nanya Technology Corporation.

NT5CC128M8FN-DII Datasheet(HTML) 18 Page - Nanya Technology Corporation.

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DDR3(L) 1Gb SDRAM
NT5CB(C)128M8FN / NT5CB(C)64M16FP(Y)
Version 1.8
18
Nanya Technology Cooperation ©
08/ 2015
All Rights Reserved.
MR0 Definition
BA2 BA1 BA0
A15-A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
↓
0
0
PPD
DLL
TM
RBT
CL
A12
A8
A3
0
0
0
1
1
1
BA1 BA0
MR select
A7
0
0
MR0
0
0
1
MR1
1
A1
A0
1
0
MR2
0
0
1
1
MR3
0
1
1
0
A11
A10
A9
1
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
A6
A5
A4
A2
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
0
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
1
WR
CAS Latency
BL
MR select
Slow exit(DLL off)
PPD
Fast exit(DLL on)
WR
DLL Reset
No
Yes
mode
Normal
Test
Reserved
Read Burst Type
Nibble Sequential
Interleave
5
6
7
8
12
14
16
10
11
10
12
Reserved
Reserved
BC4(Fixed)
BL
8(Fixed)
BC4 or 8 (on the fly)
Reserved
CAS Latency
5
Reserved
Reserved
6
7
8
9
13
14
Reserved
*1: BA2 and A13~A15 are RFU and must be programmed to 0 during MRS.
*2: WR (write recovery for autoprecharge)min in clock cycles is calculated by dividing tWR(in ns) by tCK(in ns) and rounding up to the next
integer: WRmin[cycles] = Roundup(tWR[ns] / tCK[ns]). The WR value in the mode register must be programmed to be equal or larger than
WRmin. The programmed WR value is used with tRP to determine tDAL.
*3: The table only shows the encodings for a given Cas Latency. For actual supported Cas Latency, please refer to speedbin tables for each frequency
*4: The table only shows the encodings for Write Recovery. For actual Write recovery timing, please refer to AC timingtable.



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