NT5CB64M16GP-DI datasheet(93/160 Pages) NANYA

93 / 160 page

Version 2.2

Nanya Technology Cooperation ©

04/2019

NTC Proprietary

Level: Property

DDR3(L) 1Gb SDRAM

NT5CB(C)128M8GN / NT5CB(C)64M16GP

Vref Tolerances

The dc-tolerance limits and ac-noise limits for the reference voltages VrefCA and VrefDQ are illustrated in the following

figure. It shows a valid reference voltage Vref(t) as a function of time. (Vref stands for VrefCA and VrefDQ likewise).

Vref(DC) is the linear average of Vref(t) over a very long period of time (e.g.,1 sec). This average has to meet the min/max

requirement in previous page. Furthermore Vref(t) may temporarily deviate from Vref(DC) by no more than ±1% VDD.

The voltage levels for setup and hold time measurements VIH(AC), VIH(DC), VIL(AC), and VIL(DC) are dependent on Vref.

“Vref” shall be understood as Vref(DC).

The clarifies that dc-variations of Vref affect the absolute voltage a signal has to reach to achieve a valid high or low level

and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for

Vref(DC) deviations from the optimum position within the data-eye of the input signals.

This also clarifies that the DRAM setup/hold specification and de-rating values need to include time and voltage associated

with Vref ac-noise. Timing and voltage effects due to ac-noise on Vref up to the specified limit (±1% of VDD) are included in

DRAM timing and their associated de-ratings.

Illustration of Vref(DC) tolerance and Vrefac-noise limits

Vref(DC)

Vref(DC)max

Vref(DC)min

VDD/2

Vref ac-noise

Voltage

time

VDD

VSS

VRef(t)

NT5CB64M16GP-DI Datasheet(PDF) 93 Page - Nanya Technology Corporation.