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GPLB30B Datasheet(PDF) 7 Page - Generalplus Technology Inc.

Part # GPLB30B
Description  640 Dots LCD Controller with 48KB ROM
PDF  14 Pages
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Manufacturer  GENERALPLUS [Generalplus Technology Inc.]
Direct Link  http://www.generalplus.com
Logo GENERALPLUS - Generalplus Technology Inc.

GPLB30B Datasheet(HTML) 7 Page - Generalplus Technology Inc.

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GPLB30B
© Generalplus Technology Inc.
Proprietary & Confidential
7
Apr. 16, 2009
Version: 1.1
The following figure is the GPLB30B state diagram:
HALT
OPERATING
STANDBY
CPU OFF,
32768 oscillator OFF
Wake-up or user reset
GPLB30B State Diagram
g.
The LCD driver in GPLB30B
upports 1/16 duty and 1/5 bias.
D.
The VLCD is adjustable from 2.98V to 5.75V
ith 27 levels.
etector will generate a system reset if power supply voltage
6.4. LCD Controller/Driver
The
GPLB30B
contains
a
640-dot
LCD
controller/driver.
Programmer is able to define the LCD configuration by setting the
LCD Control Register. Once the LCD configuration is completed,
the desired pattern can be displayed by filling the LCD buffer with
proper data.
The LCD driver can also operate during sleep by
keeping 32768Hz oscillator runnin
s
6.5. LCD Voltage Generator
The GPLB30B offers a voltage regulator and a charge-pumping
circuit.
The voltage regulator supplies the charge-pumping circuit
a reference voltage to generate VLCD.
Users can get the
desired VLCD by changing the output reference voltage (writing to
register) of the voltage regulator.
Enabling the voltage regulator
and charge-pumping circuit gets a stable VLCD that will not be
affected by VD
w
6.6. Low Voltage Reset
The GPLB30B provides a low voltage reset function.
The voltage
drops below 2.1V.
d
6.7. Watchdog Timer (WDT)
An on-chip watchdog timer is also available in the GPLB30B.
The WDT is designed to recover the system from abnormal
operation.
In some cases, if WDT is not cleared for one second,
the WDT will generate a system reset to restart system.
If WDT
is enabled, the WDT should be cleared through software
programming every 0.5 seconds to avoid accidental reset.
Note that the WDT only works when 32768Hz clock is activated.
6.8. Mask Options
6.8.1. 32768 oscillator
─ X’TAL32K
─ Rosc32K
6.8.2. Watchdog timer
─ Enable
─ Disable
6.8.3. PC[0:7]/SEG[39:32]
Each port/segment can be optioned as I/O or LCD segment
individually.
6.8.4. Rosc32k select
1). Built in RC
2). Built in C External R
6.8.5. System ROSC select
1). Built in RC
2). Built in C External R
6.8.6. Low voltage reset
1). Disable
2). Enable



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