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AM5728 Datasheet(PDF) 16 Page - Texas Instruments |
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AM5728 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 415 page  Copyright © 2015–2019, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: AM5729 AM5728 AM5726 16 AM5729, AM5728, AM5726 SPRS953F – DECEMBER 2015 – REVISED MAY 2019 www.ti.com Table 4-2. Ball Characteristics(1) (continued) BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PN [4] MUXMODE [5] TYPE [6] BALL RESET STATE [7] BALL RESET REL. STATE [8] BALL RESET REL. MUXMODE [9] I/O VOLTAGE VALUE [10] POWER [11] HYS [12] BUFFER TYPE [13] PULL UP/DOWN TYPE [14] DSIS [15] AF23 ddr1_d6 ddr1_d6 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AE23 ddr1_d7 ddr1_d7 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AC23 ddr1_d8 ddr1_d8 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AF27 ddr1_d9 ddr1_d9 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AD23 ddr1_dqm0 ddr1_dqm0 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AB23 ddr1_dqm1 ddr1_dqm1 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AC26 ddr1_dqm2 ddr1_dqm2 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AA27 ddr1_dqm3 ddr1_dqm3 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy V26 ddr1_dqm_ecc ddr1_dqm_ecc 0 O PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy AH25 ddr1_dqs0 ddr1_dqs0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy AE27 ddr1_dqs1 ddr1_dqs1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy AD27 ddr1_dqs2 ddr1_dqs2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy Y28 ddr1_dqs3 ddr1_dqs3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy AG25 ddr1_dqsn0 ddr1_dqsn0 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy AE28 ddr1_dqsn1 ddr1_dqsn1 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy AD28 ddr1_dqsn2 ddr1_dqsn2 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy Y27 ddr1_dqsn3 ddr1_dqsn3 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy V28 ddr1_dqsn_ecc ddr1_dqsn_ecc 0 IO PU PU 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy V27 ddr1_dqs_ecc ddr1_dqs_ecc 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 LVCMOS DDR Pux/PDy W22 ddr1_ecc_d0 ddr1_ecc_d0 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy V23 ddr1_ecc_d1 ddr1_ecc_d1 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy W19 ddr1_ecc_d2 ddr1_ecc_d2 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy W23 ddr1_ecc_d3 ddr1_ecc_d3 0 IO PD PD 1.35/1.5/1.8 vdds_ddr1 No LVCMOS DDR Pux/PDy |
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