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GD9FS1G8F2AMG Datasheet(PDF) 14 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD9FS1G8F2AMG Datasheet(HTML) 14 Page - GigaDevice Semiconductor (Beijing) Inc. |
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14 / 55 page  GD9Fx1GxF2A 14 7. BUS OPERATION There are six standard bus operations that control the device. These are Command Input, Address Input, Data Input, Data Output, Write Protect, and Standby. Typically glitches less than 5ns on Chip Enable, Write Enable and Read Enable are ignored by the memory and do not affect bus operations. CLE ALE CE# WE# RE# WP# MODE H L L Rising H X Command input for read mode L H L Rising H X Address input (4 cycles) for read mode H L L Rising H H Command input for write mode L H L Rising H H Address input (4 cycles) for write cycle L L L Rising H H Data input L L L H Falling X Sequential read and data output L L L H H X During read(busy) X X X X X H During program/Erase(busy) X X X X X L Write protect X X H X X 0V / VCC Standby Notes: 1. X can be VIL or VIH. H = Logic level HIGH. L = Logic level LOW. 2. WP# should be biased to CMOS high or CMOS low for stand-by mode. 3. WE# and RE# during Read Busy must be keep on high to prevent unplanned command/address/data input or to avert unintended data out. In this time, only Reset and Read Status can be input to the device. |
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