GD25Q16CEFG datasheet(32/68 Pages) GIGADEVICE

32 / 68 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q16C

7.23. High Performance Mode (HPM) (A3H)

The High Performance Mode (HPM) command must be executed prior to Dual or Quad I/O commands when

operating at high frequencies (see fR and fC1 in AC Electrical Characteristics). This command allows pre-charging of

internal charge pumps so the voltages required for accessing the flash memory array are readily available. The

command sequence: CS# goes lowSending A3H command Sending 3-dummy ByteCS# goes high. See

Figure28. After the HPM command is executed, HFP bit of status register will be set to 1, the device will maintain a

slightly higher standby current (Icc8) than standard SPI operation. The Release from Power-Down or HPM command (ABH)

can be used to return to standard SPI standby current (Icc1). In addition, Power-Down command (B9H) will also

release the device from HPM mode back to standard SPI standby state.

Figure28. High Performance Mode Sequence Diagram

7.24. Continuous Read Mode Reset (CRMR) (FFH)

The Dual/Quad I/O Fast Read

operations, “Continuous Read Mode” bits (M7-0) are implemented to further reduce

command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not require the

BBH/EBH/E7H command code.

Because the GD25Q16C has no hard

ware reset pin, so if Continuous Read Mode bits are set to “AXH”, the GD25Q16C

will not recognize any standard SPI commands. So Continuous Read Mode Reset command will release the Continuous

Read Mode from the “AXH” state and allow standard SPI command to be recognized. The command sequence is show in

Figure29.

Figure 29. Continuous Read Mode Reset Sequence Diagram

CS#

SCLK

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

FFH

Mode Bit Reset for Quad/Dual I/O

Don`t Care

Command

A3H

CS#

SCLK

29 30 31

MSB

3 Dummy Bytes

23 22

High Performance Mode

HPM

GD25Q16CEFG Datasheet(PDF) 32 Page - GigaDevice Semiconductor (Beijing) Inc.

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