GD25Q256DBES datasheet(13/89 Pages) GIGADEVICE

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3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q256D

WEL bit

The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When set to 1 the internal

Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or

Erase command is accepted.

TB bit

The Top Bottom (TB) bit is non-volatile (OTP). The Top/Bottom (TB) bit is used to configure the Block Protect area by

BP bit (BP3, BP2, BP1, and BP0), starting from Top or Bottom of the memory array. The TB bit

is defaulted as “0”, which

means Top area protect. When it is set to “1”, the protect area will change to Bottom area of the memory device. This bit is

written with the Write Status Register (WRSR) command.

BP3, BP2, BP1, BP0 bits

The Block Protect (BP3, BP2, BP1, and BP0) bits are non-volatile. They define the size of the area to be software

protected against Program and Erase commands. These bits are written with the Write Status Register (WRSR) command.

When the Block Protect (BP3, BP2, BP1, and BP0) bits are set to 1, the relevant memory area becomes protected against

Page Program (PP), Sector Erase (SE) and Block Erase (BE) commands. The Block Protect (BP3, BP2, BP1, and BP0)

bits can be written provided that the Hardware Protected mode has not been set. The Chip Erase (CE) command is executed

only if none sector or block is protected.

SRP1, SRP0 bits

The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP

bits control the method of the write protection: software protected, hardware protected, hardware unprotected, power supply

lock-down or one time programmable.

Table 10. Status Register Protect (SRP) bit

SRP1

SRP0

#WP

Status Register

Description

Software Protected

The Status Register can be written to after a Write Enable

command, WEL=1.(Default)

Hardware Protected

WP#=0, the Status Register locked and cannot be written to.

Hardware Unprotected

WP#=1, the Status Register is unlocked and can be written

to after a Write Enable command, WEL=1

Power Supply Lock-

Down(1)(2)

Status Register is protected and cannot be written to again

until the next Power-Down, Power-Up cycle.

One Time Program(2)

Status Register is permanently protected and cannot be

written to.

NOTE:

1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.

2. This feature is available on special order. Please contact GigaDevice for details.

QE bit

The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When

the QE bit is set to 0 (Default) the WP# pin and HOLD# / RESET# pin are enable. When the QE pin is set to 1, the Quad

IO2 and IO3 pins are enabled. (It is best to set the QE bit to 0 to avoid short issue if the WP# or HOLD# pin is tied directly

to the power supply or ground.)

GD25Q256DBES Datasheet(PDF) 13 Page - GigaDevice Semiconductor (Beijing) Inc.

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