GD25Q64CFJS datasheet(43/74 Pages) GIGADEVICE

43 / 74 page

3.3V Uniform Sector

Dual and Quad Serial Flash

GD25Q64C

7.32. Program Security Registers (42H)

The Program Security Registers command is similar to the Page Program command. Each security register contains four

pages content. A Write Enable (WREN) command must previously have been executed to set the Write Enable Latch (WEL)

bit before sending the Program Security Registers command. The Program Security Registers command is entered by

driving CS# Low, followed by the command code (42H), three address bytes and at least one data byte on SI. As soon as

CS# is driven high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the Program

Security Registers cycle is in progress, the Status Register may be read to check the value of the Write in Progress (WIP)

bit. The Write in Progress (WIP) bit is 1 during the self-timed Program Security Registers cycle, and is 0 when it is completed.

At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.

If the Security Registers Lock Bit (LB3-1) is set to 1, the Security Register will be permanently locked. Program Security

Registers command will be ignored.

Address

A23-16

A15-12

A11-10

A9-0

Security Register #1

00H

0 0 0 x

0 0

Byte Address

Security Register #2

00H

0 0 1 0

0 0

Byte Address

Security Register #3

00H

0 0 1 1

0 0

Byte Address

Figure 37. Program Security Registers command Sequence Diagram

Command

42H

CS#

SCLK

9 10

28 29 30 31

23 22 21

24-bit address

42 43 44 45

46 47

50 51 52 53

54 55

CS#

SCLK

MSB

Data Byte 2

32 33 34 35

MSB

Data Byte 1

Data Byte 3

Data Byte 256

MSB

36 37 38 39

GD25Q64CFJS Datasheet(PDF) 43 Page - GigaDevice Semiconductor (Beijing) Inc.

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